C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 109
C8051F350-TB
Manufacturer Part Number
C8051F350-TB
Description
PROTOTYPINGBOARDWITH C8051F350
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350-TB
Contents
Board
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bits 2–1: RESERVED. Read = 00. Must Write 00.
Bit 0:
ET3
R/W
Bit7
ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
RESERVED. Read = 0. Must Write 0.
ECP0: Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EADC0: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
ESMB0: Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Reserved
R/W
Bit6
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1
ECP0
R/W
Bit5
EPCA0
R/W
Bit4
Rev. 1.1
EADC0
R/W
Bit3
Reserved Reserved
R/W
Bit2
C8051F350/1/2/3
R/W
Bit1
SFR Address:
ESMB0
R/W
Bit0
0xE6
00000000
Reset Value
109
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