C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 51
C8051F350-TB
Manufacturer Part Number
C8051F350-TB
Description
PROTOTYPINGBOARDWITH C8051F350
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350-TB
Contents
Board
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bits 7–0: ADC0CLK: ADC0 Modulator Clock Divisor.
Note: The Modulator Sampling Rate is not the ADC Output Word Rate. See Section 5.1.4 for
Bits 7–3: Unused: Read = 00000b, Write = don’t care.
Bits 2–0: DECI[10:8]: ADC0 Decimation Ratio Register, Bits 10–8.
This SFR can only be modified when ADC0 is in IDLE mode.
SFR Definition 5.5. ADC0DECH: ADC0 Decimation Ratio Register High Byte
R/W
R/W
Bit7
Bit7
—
This register establishes the Modulator Clock (MDCLK), by dividing down the system clock
(SYSCLK). The input signal is sampled by the modulator at a frequency of MDCLK / 128.
For optimal performance, the divider should be chosen such that the modulator clock is
equal to 2.4576 MHz (modulator sampling rate = 19.2 kHz).
The system clock is divided according to the equation:
MDCLK = SYSCLK / (ADC0CLK + 1)
details.
This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio
determines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the
ADC0DECL register description for more information.
SFR Definition 5.4. ADC0CLK: ADC0 Modulator Clock Divisor
R/W
R/W
Bit6
Bit6
—
R/W
R/W
Bit5
Bit5
—
R/W
R/W
Bit4
Bit4
—
ADC0CLK
Rev. 1.1
R/W
R/W
Bit3
Bit3
—
DECI10
R/W
R/W
Bit2
Bit2
C8051F350/1/2/3
DECI9
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
DECI8
R/W
R/W
Bit0
Bit0
0xF7
0x9B
00000000
Reset Value
Reset Value
00000111
51
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