C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 83

• Manufacturer Part Number: C8051F350-TB
• Description: PROTOTYPINGBOARDWITH C8051F350
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F350-TB

• Contents: Board
• Processor To Be Evaluated: C8051F35x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F350
• Silicon Family Name: C8051F35x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F350
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.1.
Figure 9.3 shows the external pin connections for the comparator. The positive and negative inputs to the
comparator can each be routed to one of eight different pins using the comparator mux. Comparator out-
puts can optionally be routed to port pins using the Crossbar circuitry.
The comparator inputs (CP0+ and CP0–) are selected in the CPT0MX register (SFR Definition 9.3). The
CMX0P1–CMX0P0 bits select the comparator’s positive input; the CMX0N1–CMX0N0 bits select the com-
parator’s negative input. Important Note About Comparator Inputs: The Port pins selected as compara-
tor inputs should be configured as analog inputs in their associated Port configuration register, and
configured to be skipped by the Crossbar.
Two versions of the comparator output can be routed to port pins, using the Port I/O Crossbar. The raw
(asynchronous) comparator output CP0A is enabled using bit 5 in the XBR0 register, and will be available
at P1.4. The CP0 output (synchronized to SYSCLK) is available at P1.5 when it is enabled with bit 4 in the
XBR0 register.
Comparator0 Inputs and Outputs
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
Figure 9.3. Comparator Pin Connections
CP0 +
CP0 -
Rev. 1.1
CPT0MX
+
-
GND
VDD
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
C8051F350/1/2/3
XBR0
0
1
0
1
CP0A
CP0
P1.5
P1.4
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