C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 168
C8051F350-TB
Manufacturer Part Number
C8051F350-TB
Description
PROTOTYPINGBOARDWITH C8051F350
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350-TB
Contents
Board
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F350/1/2/3
168
1000
0100
0101
Values Read
1
0
0
0
0
0
0
0
1
X
Table 19.4. SMBus Status Decoding (Continued)
X
X
X
0
1
Current SMbus State
A master data byte was received;
ACK requested.
A slave byte was transmitted;
NACK received.
A slave byte was transmitted;
ACK received.
A Slave byte was transmitted;
error detected.
A illegal STOP or bus error was
detected while a Slave Transmis-
sion was in progress.
Rev. 1.1
Typical Response Options
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last
byte, and send STOP.
Send NACK to indicate last
byte, and send STOP fol-
lowed by START.
Send ACK followed by
repeated START.
Send NACK to indicate last
byte, and send repeated
START.
Send ACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
Send NACK and switch to
Master Transmitter Mode
(write to SMB0DAT before
clearing SI).
No action required (expect-
ing STOP condition).
Load SMB0DAT with next
data byte to transmit.
No action required (expect-
ing Master to end transfer).
Clear STO.
1
0
0
1
1
0
0
0
0
0
0
Written
Values
0
1
1
0
0
0
0
0
0
0
0
X
X
X
X
1
0
0
1
0
1
0
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