R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1077

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
7
6
5
4
Bit Name
TIE
TEIE
RIE
NAKIE
0
0
0
0
Initial
Value
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables
or disables the transmit data empty interrupt (TXI)
request.
0: Transmit data empty interrupt (TXI) request is
1: Transmit data empty interrupt (TXI) request is
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) request at the rising of the ninth clock while the
TDRE bit in ICSR is set to 1. The TEI request can be
canceled by clearing the TEND bit or the TEIE bit to 0.
0: Transmit end interrupt (TEI) request is disabled
1: Transmit end interrupt (TEI) request is enabled
Receive Interrupt Enable
This bit enables or disables the receive full interrupt
(RXI) request when receive data is transferred from
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
The RXI request can be canceled by clearing the
RDRF or RIE bit to 0.
0: Receive data full interrupt (RXI) request is disabled
1: Receive data full interrupt (RXI) request is enabled
NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
(NAKI) request when the NACKF and AL bits in ICSR
are set to 1. The NAKI request can be canceled by
clearing the NACKF or AL bit, or the NAKIE bit to 0.
0: NACK receive interrupt (NAKI) request is disabled
1: NACK receive interrupt (NAKI) request is enabled
disabled
enabled
Rev. 2.00 Sep. 24, 2008 Page 1043 of 1468
Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0412-0200