R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 516

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.5
11.5.1
(1)
In dual address mode, the transfer source address is set in EDSAR, and the transfer destination
address is set in EDDAR. One transfer operation is executed in two bus cycles. (When the data
bus width is smaller than the data access size or when the address to be accessed is not at the data
boundary of the data access size, the bus cycle is divided, resulting more than two bus cycles.)
In a transfer operation, the data on the transfer source address is read in the first bus cycle, and is
written to the transfer destination address in the next bus cycle.
These consecutive read and write cycles are indivisible: another bus cycle (external access by
another bus master, refresh cycle, or external bus release cycle) does not occur between these two
cycles.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for two consecutive bus cycles. When an idle cycle is inserted before the bus cycle, the
ETEND signal is also output in the idle cycle. The EDACK signal is not output.
Figure 11.2 shows an example of the timing in dual address mode and figure 11.3 shows the dual
address mode operation.
Rev. 2.00 Sep. 24, 2008 Page 482 of 1468
REJ09B0412-0200
Dual Address Mode
Mode Operation
Address Modes
Figure 11.2 Example of Timing in Dual Address Mode
Bφ
Address bus
RD
WR
ETEND
EXDMA read
EDSAR
cycle
EXDMA write
EDDAR
cycle