R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 610

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Data Transfer Controller (DTC)
Table 12.3 Chain Transfer Conditions
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
12.5.1
When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus
cycle is divided and the transfer data is read from or written to in bytes.
Table 12.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and
access data size. Figure 12.5 shows the bus cycle division example.
Table 12.4 Number of Bus Cycle Divisions and Access Size
Rev. 2.00 Sep. 24, 2008 Page 576 of 1468
REJ09B0412-0200
CHNE CHNS DISEL
0
0
0
1
1
1
1
SAR and DAR Values Byte (B)
Address 4n
Address 2n + 1
Address 4n + 2
2. When the contents of the CRAH is written to the CRAL in repeat transfer mode



0
1
1
1
Bus Cycle Division
1st Transfer
mode
0
0
1

0

1
Transfer
Counter*
Not 0
0*

Not 0
0*
Not 0
1 (B)
1 (B)
1 (B)
2
2
1
CHNE CHNS DISEL



0
0
0

0
0
0












2nd Transfer
1 (W)
2 (B-B)
1 (W)
Word (W)
Specified Data Size



0
0
1
0
0
1

Transfer
Counter*



Not 0
0*


Not 0
0*

2
2
1
DTC Transfer
Ends at 1st transfer
Ends at 1st transfer
Interrupt request to CPU
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Interrupt request to CPU
1 (LW)
3 (B-W-B)
2 (W-W)
Longword (LW)