R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 154

IC H8SX/1668 MCU FLASH 144LQFP

R5F61668RN50FPV

Manufacturer Part Number
R5F61668RN50FPV
Description
IC H8SX/1668 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Exception Handling
6.5
6.5.1
Instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address
error.
Table 6.5
Rev. 2.00 Sep. 24, 2008 Page 120 of 1468
REJ09B0412-0200
Type
Instruction
fetch
Stack
operation
Data read/write CPU
Data read/write DTC or
Address Error
Address Error Source
Bus Cycle
Bus Cycle and Address Error
Bus Master
CPU
CPU
DMAC
Description
Fetches instructions from even addresses
Fetches instructions from odd addresses
Fetches instructions from areas other than on-chip
peripheral module space*
Fetches instructions from on-chip peripheral
module space*
Fetches instructions from external memory space
in single-chip mode
Fetches instructions from access prohibited
area.*
Accesses stack when the stack pointer value is
even address
Accesses stack when the stack pointer value is
odd address
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-chip
mode
Accesses to access prohibited area*
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-chip
mode
Accesses to access prohibited area*
2
1
1
2
2
Address Error
No (normal)
Occurs
No (normal)
Occurs
Occurs
Occurs
No (normal)
Occurs
No (normal)
No (normal)
Occurs
Occurs
No (normal)
No (normal)
Occurs
Occurs

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