R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 594

IC H8SX/1668 MCU FLASH 144LQFP

R5F61668RN50FPV

Manufacturer Part Number
R5F61668RN50FPV
Description
IC H8SX/1668 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 Data Transfer Controller (DTC)
Figure 12.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus
connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC
transfer information.
Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR
Rev. 2.00 Sep. 24, 2008 Page 560 of 1468
REJ09B0412-0200
[Legend]
CPU interrupt request
DTC activation request
Interrupt source clear
MRA, MRB:
SAR:
DAR:
CRA, CRB:
DTCERA to DTCERF:
DTCCR:
DTCVBR:
Interrupt controller
vector number
DTCERA
DTCERF
DTCCR
request
to
must be set to 1.
(memory mapped)
External device
External
memory
8
peripheral
DTC mode registers A, B
DTC source address register
DTC destination address register
DTC transfer count registers A, B
DTC enable registers A to F
DTC control register
DTC vector base register
On-chip
On-chip
On-chip
module
ROM
ROM
Figure 12.1 Block Diagram of DTC
Bus controller
DTCVBR
REQ
ACK
DTC
Activation
Interrupt
Register
control
control
control
Bus interface
MRA
MRB
SAR
DAR
CRA
CRB

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