R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 290

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.6.7
When the DMAC or EXDMAC transfers data in single address mode, the output timing of the
DACK and EDACK signals can be changed by the DKC and EDKC bits in BCR1.
Figure 9.24 shows the output timing of the DACK and EDACK signals. The DACK and EDACK
signals are asserted a half cycle earlier by setting the DKC or EDKC bits to 1.
Rev. 2.00 Sep. 24, 2008 Page 256 of 1468
REJ09B0412-0200
DACK and EDACK Signal Output Timing
DACK or
EDACK
Read
Write
Figure 9.24 DACK and EDACK Signal Output Timing
DKC, EDCK = 0
DKC, EDCK = 1
Bφ
Address bus
CSn
AS
RD
Data bus
LHWR, LLWR
Data bus
BS
RD/WR
Notes: 1. n = 7 to 0
2. RDNn = 0
T
1
Bus cycle
Write data
T
2
Read data