R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 918

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Rev. 2.00 Sep. 24, 2008 Page 884 of 1468
REJ09B0412-0200
Bit
7
6
5
4
3
2
Bit Name
TIE
RIE
TE
RE
MPIE
TEIE
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1,a TXI interrupt request is
enabled.
A TXI interrupt request can be cancelled by reading 1
from the TDRE flag and then clearing the flag to 0, or by
clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
RXI and ERI interrupt requests can be cancelled by
reading 1 from the RDRF, FER, PER, or ORER flag and
then clearing the flag to 0, or by clearing the RIE bit to 0.
Transmit Enable
When this bit is set to 1, transmission is enabled. Under
this condition, serial transmission is started by writing
transmit data to TDR, and clearing the TDRE flag in SSR
to 0. Note that SMR should be set prior to setting the TE
bit to 1 in order to designate the transmission format.
If transmission is halted by clearing this bit to 0, the
TDRE flag in SSR is fixed 1.
Receive Enable
When this bit is set to 1, reception is enabled. Under this
condition, serial reception is started by detecting the start
bit in asynchronous mode or the synchronous clock input
in clocked synchronous mode. Note that SMR should be
set prior to setting the RE bit to 1 in order to designate
the reception format.
Even if reception is halted by clearing this bit to 0, the
RDRF, FER, PER, and ORER flags are not affected and
the previous value is retained.
Multiprocessor Interrupt Enable (valid only when the MP
bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.