R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 501

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
30
29
28
27
26
25, 24
Bit Name
EDACKE
ETENDE
EDRAKE
EDREQS
NRD

Initial
value
0
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
EDACK Pin Output Enable
In single address mode, enables or disables output
from the EDACK pin. In dual address mode, the
specification by this bit is ignored.
0: EDACK pin output disabled
1: EDACK pin output enabled
ETEND Pin Output Enable
Enables or disables output from the ETEND pin.
0: ETEND pin output disabled
1: ETEND pin output enabled
EDRAK Pin Output Enable
Enables or disables output from the EDRAK pin.
0: EDRAK pin output disabled
1: EDRAK pin output enabled
EDREQ Select
Selects whether a low level or the falling edge of the
EDREQ signal used in external request mode is
detected.
0: Low-level detection
1: Falling edge detection (the first transfer is detected
Next Request Delay
Selects the timing of the next transfer request to be
accepted.
0: Next transfer request starts to be accepted after
1: Next transfer request starts to be accepted after one
Reserved
They are always read as 0 and cannot be modified.
cycle of Bφ from the completion of the bus cycle in
progress.
on a low level after a transfer is enabled.)
transfer of the bus cycle in progress ends.
Rev. 2.00 Sep. 24, 2008 Page 467 of 1468
Section 11 EXDMA Controller (EXDMAC)
REJ09B0412-0200