R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 140

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Voltage Detection Circuit (LVD)
5.2
The registers of the voltage detection circuit are listed below.
•
•
5.2.1
The LVDCR controls the voltage-detection circuit.
LVDE, LVDRI, and LVDMON are initialized by a pin reset or power-on reset
Rev. 2.00 Sep. 24, 2008 Page 106 of 1468
REJ09B0412-0200
Bit
7
6
5
Bit
Bit name
Initial value:
R/W:
Voltage detection control register (LVDCR)
Reset status register (RSTSR)
Bit Name
LVDE
LVDRI
—
Register Descriptions
Voltage Detection Control Register (LVDCR)
LVDE
R/W
7
0
Initial Value
0
0
0
LVDRI
R/W
6
0
R/W
—
5
0
R/W
R/W
R/W
R/W
LVDMON
R
4
0
Description
LVD Enable
This bit enables or disables issuing of a reset or
interrupt by the voltage-detection circuit.
0: Disabled
1: Enabled
LVD Reset/Interrupt Select
This bit selects whether an internal reset or
interrupt is generated when the voltage detection
circuit detects a low voltage. When modifying the
LVDRI bit, ensure that low-voltage detection is in
the disabled state (the LVDE bit is cleared to 0).
0: A reset is generated when a voltage is
1: An interrupt is generated when a low voltage is
Reserved
This bit is always read as 0 and the write value
should always be 0.
detected.
detected.
R/W
—
3
0
R/W
—
2
0
R/W
—
1
0
R/W
—
0
0