HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 226

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.2
9.2.1
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an
internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer
control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
The timer counters are initialized to H'00 by a reset and in the standby modes.
9.2.2
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers (except during the T
to TCORA or TCORB). When a match is detected, the corresponding compare-match flag (CMFA
or CMFB) is set in the timer control/status register (TCSR).
The timer output signal is controlled by these compare-match signals as specified by output select
bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H'FF by a reset and in the standby modes.
194
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Register Descriptions
Timer Counter (TCNT)
Time Constant Registers A and B (TCORA and TCORB)
R/W
R/W
7
0
7
1
R/W
R/W
6
0
6
1
R/W
R/W
5
0
5
1
R/W
R/W
4
0
4
1
R/W
R/W
3
0
3
1
R/W
R/W
2
0
2
1
3
state of a write cycle
R/W
R/W
1
0
1
1
R/W
R/W
0
0
0
1