HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 356

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR2.
Bit 1: IBF
0
1
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to
0 when the host processor reads ODR2.
Bit 0: OBF
0
1
Table 14.4 shows the conditions for setting and clearing the STR2 flags.
Table 14.4 Set/Clear Timing for STR2 Flags
Flag
C/D
IBF
OBF
324
Setting Condition
Rising edge of host’s write signal (IOW)
when HA
Rising edge of host’s write signal (IOW)
when writing to IDR2
Falling edge of slave’s internal write
signal (WR) when writing to ODR2
Description
This bit is cleared when the slave processor reads IDR2
This bit is set when the host processor writes to IDR2
Description
This bit is cleared when the host processor reads ODR2
This bit is set when the slave processor writes to ODR2
0
is high
Clearing Condition
Rising edge of host’s write signal (IOW)
when HA
Falling edge of slave’s internal read signal
(RD) when reading IDR2
Rising edge of host’s read signal (IOR)
when reading ODR2
0
is low
(Initial value)
(Initial value)