HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 231

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 4—Reserved: This bit is always read as 1. It cannot be written.
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR–TCNT
compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on
the output level.
If compare-match A and B occur simultaneously, any conflict is resolved according to the
following priority order: toggle > 1 output > 0 output.
When all four output select bits are cleared to 0 the timer output signal is disabled.
After a reset, the timer output is 0 until the first compare-match event.
Bit 3: OS3
0
1
Bit 1: OS3
0
1
Bit 2: OS2
0
1
0
1
Bit 0: OS2
0
1
0
1
Description
No change when compare-match B occurs.
Output changes to 0 when compare-match B occurs.
Output changes to 1 when compare-match B occurs.
Output inverts (toggles) when compare-match B occurs.
Description
No change when compare-match A occurs.
Output changes to 0 when compare-match A occurs.
Output changes to 1 when compare-match A occurs.
Output inverts (toggles) when compare-match A occurs.
(Initial value)
(Initial value)
199