HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 324

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 3—Arbitration Lost Flag (AL): This flag indicates that arbitration was lost in master mode.
The I
at nearly the same time, if the I
AL to 1 to indicate that the bus has been taken by another master. At the same time, it sets the
IRIC bit in ICSR to generate an interrupt request.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3: AL
0
1
Bit 2—Slave Address Recognition Flag (AAS): When the addressing format is selected (FS = 0)
in slave receive mode, this flag is set to 1 if the first byte following a start condition matches bits
SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 2: AAS
0
1
292
2
C bus interface monitors the bus. When two or more master devices attempt to seize the bus
Description
Bus arbitration won
This bit is cleared to 0 at the following times:
Arbitration lost
This bit is set to 1 at the following times:
Description
Slave address or general call address not recognized
This bit is cleared to 0 at the following times:
Slave address or general call address recognized
This bit is set to 1 at the following times:
When ICDR data is written (transmit mode) or read (receive mode)
When AL is read while AL = 1, then 0 is written in AL
If the internal SDA signal and bus line disagree at the rise of SCL in master
transmit mode
If the internal SCL is high at the fall of SCL in master transmit mode
When ICDR data is written (transmit mode) or read (receive mode)
When AAS is read while AAS = 1, then 0 is written in AAS
When the slave address or general call address is detected in slave receive
mode
2
C bus interface detects data differing from the data it sent, it sets
(Initial value)
(Initial value)