HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 576

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

22.3.3
Set bits STS2 to STS0 in SYSCR as follows:
Table 22.3 Times Set by Standby Timer Select Bits (Unit: ms)
STS2
0
0
0
0
1
Note: Recommended values are printed in boldface.
544
Crystal oscillator
Set STS2 to STS0 for a settling time of at least 8 ms. Table 22.3 lists the settling times selected
by these bits at several clock frequencies.
External clock
The STS bits can be set to any value. The shortest time setting (STS2=STS1=STS0=0) is
recommended in most cases. When 1,024 states (STS2 to STS0 = 101) is selected, the
following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,
PWM timer, or watchdog timer clock, the counter in the timer will not count up normally when
1,024 states is specified for the setting time. To avoid this problem, set the STS value just
before the transition to software standby mode (before executing the SLEEP instruction), and
re-set the value of STS2 to STS0 to a value from 000 to 100 directly after software standby
mode is cleared by an interrupt.
* F-ZTAT version/ZTAT and mask-ROM versions.
STS1
0
0
1
1
0
Clock Settling Time for Exit from Software Standby Mode
STS0
0
1
0
1
0/—*
Settling
Time
(States)
8,192
16,384
32,768
65,536
131,072
16
0.51
1.0
2.0
4.1
8.2
12
0.65
1.3
2.7
5.5
10.9
10
0.8
1.6
3.3
6.6
13.1
System Clock Frequency (MHz)
8
1.0
2.0
4.1
8.2
16.4
6
1.3
2.7
5.5
10.9
21.8
4
4.1
8.2
16.4
32.8
2.0
2
4.1
8.2
16.4
32.8
65.5
1
8.2
16.4
32.8
65.5
131.1 262.1
0.5
16.4
32.8
65.5
131.1