HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 276

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to RDR.
Bit 6: RDRF
0
1
Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5: ORER
0
1
Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in
asynchronous mode. It has no meaning in synchronous mode.
Bit 4: FER
0
1
Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without
parity bits is used.
Bit 3: PER
0
1
244
Description
To clear RDRF, the CPU must read RDRF after it has been set to 1, then write
a 0 in this bit.
This bit is set to 1 when one character is received without error and transferred
from RSR to RDR.
Description
To clear ORER, the CPU must read ORER after it has been set to 1, then write
a 0 in this bit.
This bit is set to 1 if reception of the next character ends while the receive data
register is still full (RDRF = 1).
Description
To clear FER, the CPU must read FER after it has been set to 1, then write a 0
in this bit.
This bit is set to 1 if a framing error occurs (stop bit = 0).
Description
To clear PER, the CPU must read PER after it has been set to 1, then write a 0
in this bit.
This bit is set to 1 when a parity error occurs (the parity of the received data
does not match the parity selected by the O/E bit in SMR).
(Initial value)
(Initial value)
(Initial value)
(Initial value)