PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 182

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
16.2.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin while the complementary PWM
output signal is output on the P1B pin (Figure 16-5).
This mode can be used for half-bridge applications, as
shown in Figure 16-6, or for full-bridge applications
where four power switches are being modulated with
two PWM signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.2.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
FIGURE 16-6:
DS30491C-page 180
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
PIC18FXX80/XX85
P1A
P1B
PIC18FXX80/XX85
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-5:
P1A
P1B
Note 1: At this time, the TMR2 register is equal to the
td = Dead-band Delay
(2)
(2)
2: Output signals are shown as active-high.
(1)
Load
V+
V-
PR2 register.
td
Duty Cycle
V+
V-
Period
Load
td
HALF-BRIDGE PWM
OUTPUT
 2004 Microchip Technology Inc.
FET
Driver
FET
Driver
(1)
+
V
-
+
V
-
Period
(1)