PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 60

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
4.7.1
The PIC18F6585/8585/6680/8680 devices have four
two-word instructions: MOVFF,
LFSR. The second word of these instructions has the 4
MSBs set to ‘1’s and is a special kind of NOP instruction.
The lower 12 bits of the second word contain data to be
used by the instruction. If the first word of the instruc-
tion is executed, the data in the second word is
EXAMPLE 4-3:
4.8
Look-up tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
DS30491C-page 58
CASE 1:
Object Code
CASE 2:
Object Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
Look-up Tables
TWO-WORD INSTRUCTIONS
COMPUTED GOTO
TWO-WORD INSTRUCTIONS
Source Code
TSTFSZ
MOVFF
Source Code
TSTFSZ
ADDWF
ADDWF
MOVFF
CALL,
GOTO and
REG1
REG1, REG2 ; No, execute 2-word instruction
REG3
REG1
REG1, REG2 ; Yes
REG3
; is RAM location 0?
; 2nd operand holds address of REG2
; continue code
; is RAM location 0?
; 2nd operand becomes NOP
; continue code
accessed. If the second word of the instruction is exe-
cuted by itself (first word was skipped), it will execute as
a NOP. This action is necessary when the two-word
instruction is preceded by a conditional instruction that
changes the PC. A program example that demon-
strates this concept is shown in Example 4-3. Refer to
Section 25.0 “Instruction Set Summary” for further
details of the instruction set.
4.8.2
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Look-up table data may be stored 2 bytes per program
word by using table reads and writes. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory, one byte at a time.
A description of the table read/table write operation is
shown in Section 5.0 “Flash Program Memory”.
TABLE READS/TABLE WRITES
 2004 Microchip Technology Inc.