PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 287
PIC18F6680-I/L
Manufacturer Part Number
PIC18F6680-I/L
Description
Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
Manufacturer
Microchip Technology
Datasheet
1.PCM18XK1.pdf
(496 pages)
Specifications of PIC18F6680-I/L
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/AUSART/CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
64 KB
Package / Case
PLCC-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6680-I/L
Manufacturer:
RUBYCON
Quantity:
46 000
Part Number:
PIC18F6680-I/L
Manufacturer:
MICROCH
Quantity:
20 000
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23.2.2
This section describes the dedicated CAN Transmit
Buffer registers and their associated control registers.
REGISTER 23-5:
2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Mode 1, 2
DEDICATED CAN TRANSMIT
BUFFER REGISTERS
Mode 0
TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0
bit 7
Legend:
C = Clearable bit
‘1’ = Bit is set
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
TXBIF: Transmit Buffer Interrupt Flag bit
1 = Transmit buffer has completed transmission of message and may be reloaded
0 = Transmit buffer has not completed transmission of a message
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message. Clears the TXABT, TXLARB, and TXERR bits.
0 = Automatically cleared when the message is successfully sent
Unimplemented: Read as ‘0’
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
TXBIF
R/C-0
Note:
Note 1: This bit is automatically cleared when TXREQ is set.
U-0
—
2: While TXREQ is set, Transmit Buffer registers remain read-only.
3: These bits define the order in which transmit buffers will be transferred. They do not
Clearing this bit in software while the bit is set, will request a message abort.
alter the CAN message identifier.
TXABT
TXABT
R-0
R-0
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
R = Readable bit
PIC18F6585/8585/6680/8680
TXLARB
TXLARB
R-0
R-0
(2)
TXERR
TXERR
(3)
R-0
R-0
W = Writable bit
(1)
(1)
TXREQ
TXREQ
R/W-0
R/W-0
(1)
x = Bit is unknown
- n = Value at POR
U-0
U-0
—
—
TXPRI1
TXPRI1
n
R/W-0
R/W-0
DS30491C-page 285
2]
TXPRI0
TXPRI0
R/W-0
R/W-0
bit 0
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