PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 243

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To set up an asynchronous transmission:
1.
2.
3.
4.
FIGURE 18-6:
TABLE 18-6:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend:
Name
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 18.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
USART Receive Register
Baud Rate Generator Register, High Byte
Baud Rate Generator Register, Low Byte
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing
the OERR (overrun) bit to be set.
GIE/GIEH
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
—
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
ASYNCHRONOUS RECEPTION
bit
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
bit 1
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
bit 7/8
PIC18F6585/8585/6680/8680
INT0IE
CREN
SYNC
SCKP
TXIE
TXIP
Bit 4
TXIF
Stop
bit
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
Word 1
RCREG
RBIE
Bit 3
Start
bit
bit 0
TMR0IF
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
5.
6.
7.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
BRGH
FERR
Bit 2
—
Enable the transmission by setting bit TXEN
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
INT0IF
OERR
TRMT
WUE
Bit 1
bit 7/8
Word 2
RCREG
Stop
bit
TMR1IF
ABDEN
RX9D
TX9D
Bit 0
RBIF
Start
bit
0000 000x
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
bit 7/8
DS30491C-page 241
Stop
0000 000u
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
bit
Value on
all other
Resets