PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 480

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
INT Interrupt (RB0/INT).
INTCON Registers ............................................................ 111
Inter-Integrated Circuit. See I
Interrupt Sources............................................................... 345
Interrupts ........................................................................... 109
Interrupts, Flag Bits
IORLW .............................................................................. 388
IORWF .............................................................................. 388
IPR Registers .................................................................... 120
L
LFSR ................................................................................. 389
Listen Only Mode .............................................................. 328
Look-up Tables
Loopback Mode................................................................. 328
Low-Voltage Detect........................................................... 269
Low-Voltage ICSP Programming ...................................... 363
LVD. See Low-Voltage Detect.
DS30491C-page 478
SLEEP ...................................................................... 400
SUBFWP................................................................... 400
SUBLW ..................................................................... 401
SUBWF ..................................................................... 401
SUBWFB................................................................... 402
SWAPF ..................................................................... 402
TBLRD ...................................................................... 403
TBLWT ...................................................................... 404
TSTFSZ .................................................................... 405
XORLW ..................................................................... 405
XORWF..................................................................... 406
Summary Table......................................................... 368
See Interrupt Sources.
A/D Conversion Complete ........................................ 253
Capture Complete (CCP) .......................................... 170
Compare Complete (CCP) ........................................ 171
ECAN Module ........................................................... 342
INT0 .......................................................................... 124
Interrupt-on-Change
PORTB, Interrupt-on-Change ................................... 124
RB0/INT Pin, External ............................................... 124
TMR0 ........................................................................ 124
TMR0 Overflow ......................................................... 157
TMR1 Overflow ................................................. 159, 161
TMR2 to PR2 Match ................................................. 163
TMR2 to PR2 Match (PWM) ..................... 162, 173, 177
TMR3 Overflow ................................................. 164, 166
Context Saving During
Control Registers ...................................................... 111
Enable Registers....................................................... 117
Flag Registers ........................................................... 114
Logic (diagram) ......................................................... 110
Priority Registers....................................................... 120
Reset Control Registers ............................................ 123
CCP Flag (CCPxIF Bit) ............................. 169, 170, 171
Computed GOTO ........................................................ 58
Table Reads/Table Writes .......................................... 58
Characteristics .......................................................... 424
Converter Characteristics ......................................... 424
Effects of a Reset...................................................... 273
Operation .................................................................. 272
Typical Application .................................................... 269
(RB7:RB4)......................................................... 128
Interrupts........................................................... 124
Current Consumption........................................ 273
During Sleep ..................................................... 273
Reference Voltage Set Point............................. 273
2
C.
M
Master SSP I
Master SSP I
Master Synchronous Serial Port (MSSP).
Memory Organization
Memory Programming Requirements............................... 425
Migration from High-End to
Migration from Mid-Range to
MOVF ............................................................................... 389
MOVFF ............................................................................. 390
MOVLB ............................................................................. 390
MOVLW ............................................................................ 391
MOVWF ............................................................................ 391
MPLAB ASM30 Assembler,
MPLAB ICD 2 In-Circuit Debugger ................................... 409
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development
MPLAB PM3 Device Programmer .................................... 409
MPLINK Object Linker/
MSSP................................................................................ 189
Data Requirements................................................... 444
Requirements ........................................................... 443
See MSSP.
Data Memory .............................................................. 59
PIC18F8X8X Program Memory Modes ...................... 51
Program Memory ........................................................ 51
Enhanced Devices.................................................... 471
Enhanced Devices.................................................... 470
Linker, Librarian ........................................................ 408
In-Circuit Emulator .................................................... 409
In-Circuit Emulator .................................................... 409
Environment Software .............................................. 407
MPLIB Object Librarian............................................. 408
ACK Pulse ........................................................ 202, 203
Clock Stretching........................................................ 208
Clock Synchronization and the
Control Registers (general)....................................... 189
I
2
C Mode .................................................................. 198
Extended Microcontroller.................................... 51
Microcontroller .................................................... 51
Microprocessor ................................................... 51
Microprocessor with
10-bit Slave Receive Mode
10-bit Slave Transmit Mode.............................. 208
7-bit Slave Receive Mode
7-bit Slave Transmit Mode................................ 208
CKP Bit ............................................................. 209
Acknowledge Sequence Timing ....................... 222
Baud Rate Generator ....................................... 215
Bus Collision
Bus Collision During a
Bus Collision During a
Clock Arbitration ............................................... 216
Effect of a Reset ............................................... 223
I
2
C Clock Rate w/BRG ..................................... 215
2
2
C Bus
C Bus Start/Stop Bits
Boot Block .................................................. 51
(SEN = 1).................................................. 208
(SEN = 1).................................................. 208
During a Repeated
Start Condition.......................................... 224
Stop Condition .......................................... 227
Start Condition.................................. 226
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