PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 203

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 17-5:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPCON2: MSSP CONTROL REGISTER 2 (I
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master Mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enabled bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Legend:
R = Readable bit
- n = Value at POR
GCEN
Note:
R/W-0
Note:
Automatically cleared by hardware.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
ACKSTAT
R/W-0
PIC18F6585/8585/6680/8680
ACKDT
R/W-0
W = Writable bit
‘1’ = Bit is set
2
C
ACKEN
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
2
R/W-0
RCEN
C MODE)
2
C module is not in the Idle mode,
R/W-0
PEN
x = Bit is unknown
R/W-0
RSEN
DS30491C-page 201
R/W-0
SEN
bit 0