A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 85

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-110 • Minimum and Maximum DC Input and Output Levels
Table 2-111 • Minimum and Maximum DC Input and Output Levels
Table 2-112 • Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMO
S
Drive
Strength
2 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
1.2 V
LVCMOS
Drive
Strength
2 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
1.2 V
LVCMOS
Drive
Strength
2 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Min.
–0.3
Min.
–0.3
V
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2
V applications. It uses a 1.2 V input buffer and a push-pull output buffer.
V
Applicable to Advanced I/O Banks
Applicable to Standard Plus I/O Banks
Applicable to Standard I/O Banks
Min.
–0.3
V
VIL
0.35 * VCCI 0.65 * VCCI
VIL
0.35 * VCCI 0.65 * VCCI 1.26
VIL
0.35 * VCCI 0.65 * VCCI 1.26
Max.
Max.
V
V
Max.
V
Min.
Min.
V
V
Min.
V
VIH
VIH
VIH
Max.
Max.
1.26
V
V
Max.
V
0.25 * VCCI 0.75 * VCCI 2
0.25 * VCCI 0.75 * VCCI 2
0.25 * VCCI 0.75 * VCCI 2
Max.
R e v i s i o n 9
Max.
VOL
V
V
V
OL
Max.
VOL
V
VOH
VOH
Min.
Min.
V
V
VOH
Min.
V
mA mA
mA mA
I
I
OL
OL
mA mA
I
OL
ProASIC3L Low Power Flash FPGAs
I
I
OH
OH
2
2
I
OH
2
I
I
Max.
Max.
TBD
OSH
OSH
TBD
mA
mA
I
Max.
TBD
OSH
mA
1
1
1
I
I
Max.
Max.
TBD
TBD
OSL
OSL
mA
I
mA
Max.
TBD
OSL
mA
1
1
1
I
µA µA
I
I
µA µA
µA µA
IL
10 10
10 10
IL
10 10
IL
2
2
2
I
I
I
2- 71
IH
IH
IH
2
2
2