HC230F1020 Altera, HC230F1020 Datasheet - Page 148

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
## Signal-Ball Assignments
set_location_assignment PIN_AH5 -to addr_out[0]
set_location_assignment PIN_AH6 -to addr_out[1]
set_location_assignment PIN_AJ5 -to data_in[0]
set_location_assignment PIN_AJ6 -to data_in[1]
set_location_assignment PIN_AJ32 -to resetn
set_location_assignment PIN_AM17 -to ref_clk
# I/O Type and Parameter Assignments
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to addr_out[0]
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to addr_out[1]
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to data_in[0]
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to data_in[1]
set_instance_assignment -name IO_STANDARD LVDS -to resetn
set_instance_assignment -name IO_STANDARD LVCMOS -to ref_clk
set_instance_assignment -name fast_input_register on -to data_in[0]
set_instance_assignment -name fast_input_register on -to data_in[1]
set_instance_assignment -name fast_output_register on -to addr_out[0]
set_instance_assignment -name fast_output_register on -to addr_out[1]
set_instance_assignment -name output_pin_load 10 -to addr_out[0]
set_instance_assignment -name output_pin_load 10 -to addr_out[1]
set_instance_assignment -name current_strength_new 16mA -to addr_out[0]
set_instance_assignment -name stratixii_termination “series 25 ohms without calibration”\
-to data_in[1]
Assigning
Timing
Constraints
6–20
I/O Assignment Example Script
The following Tcl script example specifies several different I/O
constraints.
Planning Design Timing Constraints
Timing constraints ensure that a design compiled in the Quartus II
software meets specific timing requirements. When you target an FPGA,
you may decide not to apply a complete set of timing constraints,
choosing instead to fix any timing problems in your prototype system if
and when they arise. HardCopy devices, however, cannot be modified
using reconfiguration to fix timing problems, so it is critically important
that a design is fully constrained. Designs not fully constrained would
result in significantly different timing characteristics between the
prototype Stratix II FPGA and the HardCopy II device. By fully
constraining a design, Altera can guarantee that both the Stratix II FPGA
and the HardCopy II device fully complies with your timing
specifications.
Altera Corporation
September 2008