HC230F1020 Altera, HC230F1020 Datasheet - Page 162

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
## End of global_assignments.tcl
## pin_assignments.tcl
set_location_assignment PIN_AH5 -to addr_out[0]
set_location_assignment PIN_AH6 -to addr_out[1]
set_location_assignment PIN_AJ5 -to data_in[0]
set_location_assignment PIN_AJ6 -to data_in[1]
set_location_assignment PIN_AJ32 -to resetn
set_location_assignment PIN_AM17 -to ref_clk
## I/O Type and Parameter Assignments
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to addr_out[0]
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to addr_out[1]
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to data_in[0]
set_instance_assignment -name IO_STANDARD "1.5-V HSTL CLASS II" -to data_in[1]
set_instance_assignment -name IO_STANDARD LVDS -to resetn
set_instance_assignment -name IO_STANDARD LVCMOS -to ref_clk
set_instance_assignment -name fast_input_register on -to data_in[0]
set_instance_assignment -name fast_input_register on -to data_in[1]
set_instance_assignment -name fast_output_register on -to addr_out[0]
set_instance_assignment -name fast_output_register on -to addr_out[1]
set_instance_assignment -name output_pin_load 10 -to addr_out[0]
set_instance_assignment -name output_pin_load 10 -to addr_out[1]
## End of pin_assignments.tcl
6–34
Pin Assignments Script pin_assignments.tcl
The pin_assignments.tcl script run from the top-level script,
demo_design.tcl, specifies top-level design signal to package ball
assignments and I/O parameters:
TimeQuest Constraint File demo_design.sdc
TimeQuest reads the SDC file demo_design.sdc and applies timing
constraints for the system clock, ref_clk, and I/O-to-core timing
specifications.
## constraints.sdc
create_clock –period 10.0 MHz -name ref_clk [get_ports ref_clk]
set_clock_latency -late 3 ref_clk
set_clock_latency -early 2 ref_clk
set_clock_uncertainty –hold –to ref_clk 0.250
set_clock_uncertainty –setup –to ref_clk 0.250
# Input delay of 6ns (max) & 2ns (min) for bus data_in[1:0]
set_input_delay –clock ref_clk –max 6 [get_ports data_in]
Altera Corporation
September 2008