HC230F1020 Altera, HC230F1020 Datasheet - Page 182

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

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HardCopy Series Handbook, Volume 1
7–18
Figure 7–9. Internal Input Delay Specification (Setup)
Figure 7–10
Figure 7–10. Internal Input Delay Specification (Hold)
Primary Output Port Timing
You must specify the output port timing constraint for every primary
output port in the design and for the output path of every bidirectional
port. There are two ways to capture the output port timing, as described
in the following two sections.
data
data
clk
clk
shows a generic circuit with an on-chip hold-time constraint.
Delay
Delay
Data
Path
Data
Path
tsu for a Primary Input Port
tH for a Primary Input
Delay
Delay
Clock
Clock
Altera Corporation
September 2008
tsu
tH