HC230F1020 Altera, HC230F1020 Datasheet - Page 74

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HC230F1020

Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet

Specifications of HC230F1020

Lead Free Status / RoHS Status
Not Compliant

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HardCopy Series Handbook, Volume 1
4–32
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Differential
SSTL18 class II
1.8-V differential
HSTL class I
1.8-V differential
HSTL class II
1.5-V differential
HSTL class I
1.5-V differential
HSTL class II
Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices
I/O Standard
The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology on
row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to
5 pF.
CLK [1, 3, 9, 11]
This is the default setting in the Quartus II software if supported by the pin location.
The PCI clamping diode is only supported on the top and bottom I/O pins.
Like Stratix II devices, differential HSTL and SSTL is supported only on the column
interface
These numbers are preliminary and pending further silicon characterization.
Table
DQS
(5)
(5)
(5)
(5)
4–36:
(5)
IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL.
20 mA
12 mA
20 mA
12 mA
20 mA
Strength
16 mA
18 mA
10 mA
16 mA
18 mA
10 mA
16 mA
18 mA
Drive
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
(3)
(3)
(3)
(3)
(3)
and
Interface
Memory
FPLL_CLK
IOEs
140
220
220
220
210
210
220
250
270
190
200
210
150
160
170
180
190
170
170
170
Speed
High
are dedicated input clocks, and excluded from this table.
IOEs
Column
Bottom
General Purpose
IOEs
Right
Row
CLK [0,
10]
2, 8,
(2)
Notes
CLK
12..15]
[4..7,
CLK
140
220
220
220
210
210
220
250
270
190
200
210
150
160
170
180
190
170
170
170
,
(1),
PLL_OUT
Altera Corporation
(6)
September 2008
PLL_OUT
(Part 4 of 4)
140
220
220
220
210
210
220
250
270
190
200
210
150
160
170
180
190
170
170
170
and memory
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit

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