HC230F1020 Altera, HC230F1020 Datasheet - Page 167

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
programmable ALMs in Stratix II devices to fine-grain HCell macros in
HardCopy II devices. All ALM functions are re-mapped to HCells in
HardCopy II devices. Using fine-grain HCells eliminates the need for the
programmable routing multiplexers (MUXs) found inside the Stratix II
ALM blocks. This reduces the number of levels of logic required to
implement ALM functions from the Stratix II device. Consequently, the
transport, or propagation, delays associated in the Stratix II FPGA with
ALMs in register-to-register paths are smaller in the HardCopy II device.
The HardCopy II device does not require configuration SRAM, so die size
is significantly smaller than for Stratix II counterpart devices. One effect
of reduced die size is that overall routing length is shorter. In addition,
HardCopy II devices use customization of metal layers 5 and 6 to
implement user-logic connections. The fact that no configuration SRAM
is required eliminates the need for SRAM-configurable routing switches
and programmable connection points, all of which adversely affect
timing. Therefore, overall, parasitic capacitance and resistance and
crosstalk levels are often lower in the HardCopy II device, leading to
faster connections than those found in the Stratix II FPGA.
Faster logic element implementation and faster routing in HardCopy II
devices generally result in faster register-to-register paths and higher
overall clock frequencies. Software place-and-route tools have a
significant impact on timing results, however, so there are cases where
Stratix II register-to-register paths are faster than the corresponding paths
in the HardCopy II device.
The internal timing performance of digital signal processing (DSP)
functions is similar in a Stratix II FPGA and its corresponding
HardCopy II device. In Stratix II FPGAs, DSP functions are usually
implemented in the embedded DSP blocks. These DSP blocks provide
optimal area and performance for DSP functions. In HardCopy II devices,
the same DSP functions are implemented in HCell DSP macros, which are
designed to match the functionality and timing of the DSP blocks in
Stratix II devices. However, the timing performance of paths between the
DSP functions and other core logic is generally faster in the HardCopy II
device than in the Stratix II FPGA.
RAM-block access time is similar in a Stratix II FPGA and its
corresponding HardCopy II device. However, as for DSP functions, the
timing performance of paths between the RAM blocks and other core
logic is generally faster in the HardCopy II device than in the Stratix II
FPGA.
Introduction
7–3