HC230F1020 Altera, HC230F1020 Datasheet - Page 78

no-image

HC230F1020

Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet

Specifications of HC230F1020

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HC230F1020
Manufacturer:
ALTERA
0
Part Number:
HC230F1020AJ
Manufacturer:
ALTERA
0
Part Number:
HC230F1020ANQ
Manufacturer:
Discera
Quantity:
2 000
Part Number:
HC230F1020AW
Manufacturer:
ALTERA
0
Part Number:
HC230F1020BA
Manufacturer:
ALTERA
0
Part Number:
HC230F1020BL
Manufacturer:
ALTERA
0
HardCopy Series Handbook, Volume 1
4–36
W
t
t
Timing unit interval (TUI)
f
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t
t
f
f
f
f
TCCS
SW
Output jitter
RISE
FALL
HSDR
HSDRDPA
DUTY
LOCK
HSCLK
HSCLK
HSDR
HSDRDPA
Table 4–39. HighSpeed Timing Specifications and Definitions (Part 2 of 2)
Table 4–40. HardCopy II High-Speed I/O Specifications for HC210W Device
HighSpeed Timing Specifications
(data rate)
(clock frequency)
= f
Symbol
(DPA data rate)
HSDR
/ W
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 t(LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
All differential standards
All differential standards
Table 4–40
F484 WireBond devices.
PLL multiplication factor
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
Maximum/minimum LVDS data transfer rate (f
Maximum/minimum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the
TCCS measurement.
The period of time during which the data must be valid in order to
capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.
Peak-to-peak input jitter on highspeed PLLs.
Peak-to-peak output jitter on highspeed PLLs.
Duty cycle on highspeed transmitter output clock.
Lock time for highspeed transmitter and receiver PLLs.
shows the high-speed I/O timing specifications for HC210W
Conditions
Definitions
Min
150
150
150
400
16
16
(4)
(4)
Notes
HSDR
HSDRDPA
Typ
(1),
= 1/TUI), non-DPA.
(2)
Altera Corporation
Max
320
320
320
640
640
320
640
240
= 1/TUI), DPA.
(5)
September 2008
(Part 1 of 2)
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
Unit
ps
ps
ps

Related parts for HC230F1020