HC230F1020 Altera, HC230F1020 Datasheet - Page 64

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
Maximum Input
Clock Rates
4–22
Note to
(1)
C
C
C
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL2 class I
SSTL2 class II
SSTL18 class I
SSTL18 class II
1.5 V HSTL class I
1.5 V HSTL class II
1.8 V HSTL class I
1.8 V HSTL class II
PCI
Table 4–32. HardCopy II Device Capacitance
Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part
1 of 2)
Symbol
CLKLR
CLKLR+
OUTFB
(1)
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ± 0.5 pF.
Table
I/OStandard
Input capacitance on left/right clock
inputs CLK0, CLK2, CLK8, CLK10.
Input capacitance on left/right clock
inputs CLK1, CLK3, CLK9, and CLK11.
Input capacitance on dual-purpose clock
output/feedback pins in PLL banks 9, 10,
11, and 12.
4–32:
Parameter
Tables 4–33
HardCopy II I/Os.
Interface
Memory
IOEs
500
500
500
500
500
500
500
500
500
500
500
500
500
500
Speed
High
IOEs
and
500
500
500
500
500
—
—
—
—
—
—
—
—
—
4–34
Note (1)
Purpose
General
IOEs
500
500
500
500
500
500
show the maximum input clocking rates of
—
—
—
—
—
—
—
—
HC210W
Typical
4.3
4.2
6.9
(Part 2 of 2)
8..11]
[0..3,
CLK
500
500
500
500
500
—
—
—
—
—
—
—
—
—
HC210, HC220,
HC230, HC240
12..15]
[4..7,
Typical
CLK
500
500
500
500
500
500
500
500
500
500
500
500
500
500
6.1
3.3
6.7
FPLL_CLK PLL_FB
500
500
500
500
500
—
—
—
—
—
—
—
—
—
Altera Corporation
September 2008
500
500
500
500
500
500
500
500
500
500
500
500
500
500
Unit
pF
pF
pF
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit