HC230F1020 Altera, HC230F1020 Datasheet - Page 21

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Clock multiplication and division
Phase shift
Clock switchover
PLL reconfiguration
Reconfigurable bandwidth
Spread-spectrum clocking
Programmable duty cycle
Number of clock outputs per PLL
Number of dedicated external clock outputs
per PLL
Number of feedback clock inputs per PLL
Table 2–7. HardCopy II PLL Features
For enhanced PLLs, m and n range from 1 to 512 and post-scale counters range from 1 to 512 with 50% duty cycle.
For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256.
For fast PLLs, n can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle
clock outputs, post-scale counters range from 1 to 16.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The
supported phase shift range is from 125 to 250 ps. HardCopy II devices can shift all output frequencies in
increments of at least 45
parameters. For non-50% duty cycle clock outputs post-scale counters range from 1 to 256.
HardCopy II fast PLLs only support manual clock switchover.
The clock outputs can be driven to internal clock networks or to a pin.
The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For
high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock
(txclkout
If the design uses external feedback input pins, you will lose one (or two, if f
clock output pin.
Table
2–7:
)
.
Feature
°
. Smaller degree increments are possible depending on the frequency and divide
PLL functionality in HardCopy II devices remains the same as in Stratix II
FPGA PLLs. Therefore, the HardCopy II PLLs support PLL
reconfiguration (the PLL can be dynamically configured in user mode).
HardCopy II enhanced and fast PLLs support a one-to-one mapping from
Stratix II PLL resources.
PLLs. For more information on the Stratix II PLL features, refer to the
Stratix II Device Handbook.
(5)
Down to 125-ps increments
Three differential or six singled-
ended
m/(n × post-scale counter)
Enhanced PLL
Table 2–7
1
v
v
v
v
v
6
(7)
shows the features of the different
(1)
(3)
BIN
Down to 125-ps increments
is differential) dedicated external
m/(n × post-scale counter)
PLLs and Clock Networks
Fast PLL
v
v
v
v
(6)
4
(4)
Preliminary
2–13
(2)
(3)