HC230F1020 Altera, HC230F1020 Datasheet - Page 65

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
PCI-X
Differential SSTL2 class I
(2),
Differential SSTL2 class II
(2),
Differential SSTL18 class I
(2),
Differential SSTL18 class II
(2),
1.8-V Differential HSTL
class I (2),
1.8-V Differential HSTL
class II (2),
1.5-V Differential HSTL
class I (2),
1.5-V Differential HSTL
class II (2),
LVDS
LVPECL
HyperTransport
Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part
2 of 2)
(3)
(3)
(3)
(3)
The PCI clamping diode is only supported on the top and bottom I/O pins.
This I/O standard is only supported on the DQS, CLK, and PLL_FB input pins.
For HC210 and HC220, differential HSTL/SSTL input is supported on top/bottom PLL_FB, the top clock pins and
DQS pins located on the top I/Os.
(1)
I/OStandard
Table
(3)
(3)
(3)
(3)
4–33:
Interface
Memory
IOEs
500
500
500
500
500
500
500
500
500
—
—
—
Speed
High
IOEs
520
520
—
—
—
—
—
—
—
—
—
—
Purpose
General
IOEs
500
—
—
—
—
—
—
—
—
—
—
—
8..11]
[0..3,
CLK
717
717
—
—
—
—
—
—
—
—
—
—
12..15]
[4..7,
CLK
500
500
500
500
500
500
500
500
500
450
450
—
FPLL_CLK PLL_FB
Maximum Input Clock Rates
717
717
—
—
—
—
—
—
—
—
—
—
500
500
500
500
500
500
500
500
500
450
450
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
4–23