HC230F1020 Altera, HC230F1020 Datasheet - Page 84

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
External
Memory
Interface
Specifications
4–42
Note to
(1)
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
t
DDR
DDR2
QDRII
RLDRAMII
ARESET_RECONFIG
Table 4–43. HardCopy II Fast PLL Specifications (Part 2 of 2)
Table 4–44. HardCopy II Maximum Clock Rate Support for External Memory Interfaces
Memory Standards
Limited by I/O f
HardCopy II devices do not support PLL-based external memory interface except for SDR SDRAMs which do not
require the DLL.
HC210W supports memory interface on the top I/O banks.
HC210 and HC220 support memory interface on the top I/O banks. HC230 and HC240 support memory interface
on the top and bottom I/O banks.
You will need to under-clock a 300 MHz memory device.
You will need to under-clock a 250 MHz memory device.
Based on a DDIO scheme with the 1.8-V HSTL I/O standard.
Based on the PLL dedicated scheme. Use the same F
write-side is limited by the new tDS/tH specification.
Name
(7)
(6)
Table
Table
(6)
4–43:
4–44:
Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the
PLL after scan done goes high.
MAX
.
Table 4–44
can support with external memory devices.
Wire Bond Package
Com (C)
150
150
150
150
HC210W
Description
summarizes the maximum clock rate that HardCopy II devices
Ind (I)
(2)
133
133
133
133
MAX
HardCopy II Device
HC210 / HC220 / HC230 / HC240
specification for Static-PHY and Auto-PHY since the
Com (C)
250
200
267
250
(4)
Flip Chip Package
Min
500
Typ
—
233
233
Ind (I)
200
233
(5)
(4)
Altera Corporation
(3)
Note (1)
September 2008
Max
—
MHz
MHz
MHz
MHz
Unit
Unit
ns