HC230F1020 Altera, HC230F1020 Datasheet - Page 33

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
High-Speed IOE
High-speed IOEs in HC210, HC220, and HC230 devices are located on the
left side of the device. High-speed IOEs in HC240 devices are located on
the left and right sides of the device. (Directions are based on a top view
of the silicon die.) Unlike Stratix II left and right side I/O pins,
HardCopy II left and right side I/O pins do not support SSTL or HSTL
I/O standards or the PCI clamping diode. In Stratix II FPGAs, the right
and left IOEs support the high-speed IOE features.
The high-speed IOE has many features, including:
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The following I/O standards are supported when using high-speed IOEs:
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Dedicated single-ended I/O buffers
Differential I/O buffer
JTAG BST support
On-chip driver series termination (non-calibrated)
On-chip termination for differential I/O standards
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Open-drain outputs
Transmit serializer
Receive deserializer
Dynamic phase alignment (DPA)
Double data rate (DDR) registers
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
LVDS
HyperTransport technology
I/O Structure and Features
Preliminary
2–25