CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 12

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write
(IOWR, IOWX) instructions. IORD reads the selected port into
the accumulator. IOWR writes data from the accumulator to the
selected port. Indexed I/O Write (IOWX) adds the contents of X
to the address in the instruction to form the port address and
writes data from the accumulator to the specified port. Note that
Table 1. I/O Register Summary
Document #: 38-08028 Rev. *D
Port 0 Data
Port 1 Data
Port 2 Data
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
Port 0 Mode0
Port 0 Mode1
Port 1 Mode0
Port 1 Mode1
USB Device Address
EP0 Counter Register
EP0 Mode Register
EP1 Counter Register
EP1 Mode Register
USB Status & Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer (LSB)
Timer (MSB)
WDR Clear
Clock Configuration
Processor Status & Control
Register Name
I/O Address
0x0C
0x0D
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x0A
0x0B
0x10
0x12
0x13
0x14
0x1F
0x20
0x21
0x24
0x25
0x26
0xF8
0xFF
0x11
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
R
R
R
GPIO Port 0
GPIO Port 1
Auxiliary input register for D+, D–, VREG, XTALIN,
XTALOUT
Interrupt enable for pins in Port 0
Interrupt enable for pins in Port 1
Interrupt polarity for pins in Port 0
Interrupt polarity for pins in Port 1
Controls output configuration for Port 0
Controls output configuration for Port 1
USB Device Address register
USB Endpoint 0 counter register
USB Endpoint 0 configuration register
USB Endpoint 1 counter register
USB Endpoint 1 configuration register
USB status and control register
Global interrupt enable register
USB endpoint interrupt enables
Lower 8 bits of free-running timer (1 MHz)
Upper 4 bits of free-running timer
Watch Dog Reset clear
Internal / External Clock configuration register
Processor status and control
specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O
port is selected solely by the contents of X.
Note: All bits of all registers are cleared to all zeros on reset,
except the Processor Status and Control Register (Figure 22). All
registers not listed are reserved, and should never be written by
firmware. All bits marked as reserved should always be written
as 0 and be treated as undefined by reads.
Function
CY7C63221/31A
Page 12 of 47
Fig.
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26
29
10
14
17
15
17
16
23
24
19
20
22
11
6
8
9
3
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