CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 31

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Bit [7:0]: P0 [7:0] Interrupt Enable
Document #: 38-08028 Rev. *D
Read/Write
Read/Write
Bit Name
Bit Name
1 = Enables GPIO interrupts from the corresponding input pin.
Reset
Reset
Bit #
Bit #
Int
Wake-up
USB-
PS/2
Int
EP1
Int
1
1
1
D
D
CLK
CLK
CLK
D
W
CLR
CLR
7
0
7
0
CLR
-
Q
Q
Q
(Reg 0x21)
Enable [1]
(Reg 0x20)
(Reg 0x20)
Enable [0]
Enable [7]
Figure 26. Port 0 Interrupt Enable Register (Address 0x04)
W
Figure 27. Port 1 Interrupt Enable Register (Address 0x05)
6
0
6
0
-
Figure 25. Interrupt Controller Logic Block Diagram
W
5
0
5
0
-
Reserved
GPIO CLR
USB-PS/2 IRQ
128-μs CLR
128-μs IRQ
1-ms CLR
1-ms IRQ
EP1 CLR
EP1 IRQ
GPIO IRQ
EP0 CLR
EP0 IRQ
Wake-up CLR
USB-PS/2 Clear
Wake-up IRQ
P0 Interrupt Enable
W
4
0
4
0
-
Interrupt
Encoder
Priority
0 = Disables GPIO interrupts from the corresponding input
pin.
Interrupt
IRQout
Vector
W
3
0
3
0
-
Acknowledge
CPU
To CPU
Interrupt
Interrupt
Enable
Global
W
CLR
2
0
2
0
-
Bit
Controlled by DI, EI, and
RETI Instructions
P1[1:0] Interrupt Enable
CY7C63221/31A
W
W
1
0
1
0
IRQ Pending
(Bit 7, Reg 0xFF)
Int Enable
Sense
(Bit 2, Reg 0xFF)
IRQ
Page 31 of 47
W
W
0
0
0
0
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