CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 17

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 2. Wake-up Timer Adjust Settings
General Purpose I/O Ports
Ports 0 and 1 provide up to 10 versatile GPIO pins that can be read or written (the number of pins depends on package type).
Port 0 is an 8-bit port; Port 1 contains 2 bits, P1.1–P1.0 in the
and CY7C63221A-XC parts. Each bit can also be selected as an
interrupt source for the microcontroller.
The data for each GPIO pin is accessible through the Port Data
Register. Writes to the Port Data Register store outgoing data
state for the port pins, while reads from the Port Data Register
return the actual logic value on the port pins, not the Port Data
Register contents.
Document #: 38-08028 Rev. *D
(Bits [6:4] in Figure 3)
Internal
Data Bus
Adjust Bits [2:0]
000 (reset state)
001
010
011
100
101
110
111
See Section for the value of t
GPIO
Mode
Interrupt
Polarity
Interrupt
Enable
Port Write
Data
Out
Register
Figure 5. Block Diagram of GPIO Port (one pin shown)
Port Read
2
WAKE
Wake-up Time
Interrupt
128 * t
Logic
16 * t
32 * t
64 * t
1 * t
2 * t
4 * t
8 * t
WAKE
WAKE
WAKE
WAKE
WAKE
WAKE
WAKE
WAKE
Threshold Select
Each GPIO pin is configured independently. The driving state of
each GPIO pin is determined by the value written to the pin’s
Data Register and by two associated pin’s Mode0 and Mode1
bits.
The Port 0 Data Register is shown in Figure 6, and the Port 1
Data Register is shown in Figure . The Mode0 and Mode1 bits
for the two GPIO ports are given in Figure 8 through Figure 11.
To Interrupt
Controller
Q1
Q2
14 kΩ
V
CC
Q3
GPIO
Pin
CY7C63221/31A
Page 17 of 47
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