CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 23

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

USB Device
The supports one USB Device Address with two endpoints: EP0
and EP1.
In either USB or PS/2 mode, this register is cleared by both hard-
ware resets and the USB bus reset. See Section for more infor-
mation on the USB Bus Reset - PS/2 interrupt.
Bit 7: Device Address Enable
The SIE provides a locking feature to prevent firmware from
overwriting bits in the USB Endpoint 0 Mode Register. Writes to
the register have no effect from the point that Bit[6:0] of the
register are updated (by the SIE) until the firmware reads this
register. The CPU can unlock this register by reading it.
Because of these hardware-locking features, firmware should
perform an read after a write to the USB Endpoint 0 Mode
Register and USB Endpoint 0 Count Register
verify that the contents have changed as desired, and that the
SIE has not updated these values.
Bit [7:4] of this register are cleared by any non-locked write to
this register, regardless of the value written.
Document #: 38-08028 Rev. *D
Read/Write
Read/Write
Bit Name
Bit Name
This bit must be enabled by firmware before the serial inter-
face engine (SIE) will respond to USB traffic at the address
specified in Bit [6:0].
1 = Enable USB device address.
0 = Disable USB device address.
Reset
Reset
Bit #
Bit #
Received
Address
SETUP
Device
Enable
R/W
R/W
7
0
7
0
Received
R/W
R/W
IN
6
0
6
0
Figure 14. USB Device Address Register (Address 0x10)
Figure 15. Endpoint 0 Mode Register (Address 0x12)
Received
(Figure
OUT
R/W
R/W
5
0
5
0
17) to
Transaction
ACKed
R/W
R/W
4
0
4
0
USB Address Register
The USB Device Address Register contains a 7-bit USB address
and one bit to enable USB communication. This register is
cleared during a reset, setting the USB device address to zero
and marking this address as disabled.
format of the USB Address Register.
Device Address Bit
Bit [6:0]: Device Address Bit[6:0]
USB Control Endpoint
All USB devices are required to have an endpoint number 0
(EP0) that is used to initialize and control the USB device. EP0
provides access to the device configuration information and
allows generic USB status and control accesses. EP0 is bidirec-
tional, as the device can both receive and transmit data. EP0
uses an 8-byte FIFO at SRAM locations 0xF8-0xFF, as shown in
Section .
The EP0 endpoint mode register uses the format shown in
Figure
Bit 7: SETUP Received
These bits must be set by firmware during the USB enumer-
ation process (i.e., SetAddress) to the non-zero address as-
signed by the USB host.
1 = A valid SETUP packet has been received. This bit is
forced HIGH from the start of the data packet phase of the
SETUP transaction until the start of the ACK packet returned
by the SIE. The CPU is prevented from clearing this bit during
this interval. While this bit is set to ‘1’, the CPU cannot write
to the EP0 FIFO. This prevents firmware from overwriting an
incoming SETUP transaction before firmware has a chance
to read the SETUP data.
0 = No SETUP received. This bit is cleared by any non-locked
writes to the register.
15.
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
Mode Bit
R/W
R/W
CY7C63221/31A
1
0
1
0
Figure 14
shows the
Page 23 of 47
R/W
R/W
0
0
0
0
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