CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 15

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

record the occurrence of LVR/BOR and WDR respectively. The
firmware can interrogate these bits to determine the cause of a
reset.
The microcontroller begins execution from ROM address 0x0000
after a LVR, BOR, or WDR reset. Although this looks like interrupt
vector 0, there is an important difference. Reset processing does
NOT push the program counter, carry flag, and zero flag onto
program stack. Attempting to execute either a RET or RETI in
the reset handler will cause unpredictable execution results.
The following events take place on reset. More details on the
various resets are given in the following sections.
Low-voltage Reset (LVR)
When V
started and the Low-voltage Reset is initially enabled by default.
At the point where V
the value of V
The Watchdog Timer Reset (WDR) occurs when the internal Watchdog timer rolls over. Writing any value to the write-only Watchdog
Reset Register at address 0x26 will clear the timer. The timer will roll over and WDR will occur if it is not cleared within t
Figure 4) of the last clear. Bit 6 (Watchdog Reset bit) of the Processor Status and Control Register is set to record this event (see
Section for more details). A Watchdog Timer Reset lasts for typically 2–4 ms after which the microcontroller begins execution at ROM
address 0x0000.
Document #: 38-08028 Rev. *D
1. All registers are reset to their default states (all bits cleared,
2. GPIO and USB pins are set to high-impedance state.
3. The VREG pin is set to high-impedance state.
4. Interrupts are disabled.
5. USB operation is disabled and must be enabled by firmware
6. For a BOR or LVR, the external oscillator is disabled and
7. The Program Stack Pointer (PSP) and Data Stack Pointer
8. Program execution begins at address 0x0000 after the appro-
except in Processor Status and Control Register).
if desired, as explained in Section .
Internal Clock mode is activated, followed by a time-out period
t
mode, and there is no delay for V
Note that the External Oscillator Enable (Bit 0, Figure 3) will
be cleared by a WDR, but it does not take effect until suspend
mode is entered.
(DSP) reset to address 0x00. Firmware should move the DSP
for USB applications, as explained in Section .
priate time-out period.
START
CC
for V
is first applied to the chip, the internal oscillator is
LVR
CC
), an internal counter starts counting for a period
WDR
to stabilize. A WDR does not change the clock
CC
has risen above V
since last write to WDR
At least 10.1 ms
t
WATCH = 10.1 to
(at F
14.6 ms
CC
OSC
stabilization on a WDR.
Figure 4. Watchdog Reset (WDR, Address 0x26)
LVR
= 6 MHz)
(see Section for
WDR goes HIGH
for 2–4 ms
2–4 ms
of t
time, the microcontroller enters a partial suspend state to wait for
V
0x0000.
As long as the LVR circuit is enabled, this reset sequence
repeats whenever the V
LVR can be disabled by firmware by setting the Low-voltage
Reset Disable bit in the Clock Configuration Register (Figure 3).
In addition, the LVR is automatically disabled in suspend mode
to save power. If the LVR was enabled before entering suspend
mode, it becomes active again once the suspend mode ends.
When LVR is disabled during normal operation (e.g., by writing
‘0’ to the Low-voltage Reset Disable bit in the Clock Configu-
ration Register), the chip may enter an unknown state if V
drops below V
during normal operation. If LVR is disabled (e.g., by firmware or
during suspend mode), a secondary low-voltage monitor, BOR,
becomes active, as described in the next section. The LVR/BOR
Reset bit of the Processor Status and Control Register
(Figure 22), is set to ‘1’ if either a LVR or BOR has occurred.
Brown-out Reset (BOR)
The Brown-out Reset (BOR) circuit is always active and behaves
like the POR. BOR is asserted whenever the V
device is below an internally defined trip voltage of approximately
2.5V. The BOR re-enables LVR. That is, once V
trips BOR, the part remains in reset until V
At that point, the t
resumes, and the microcontroller starts executing code from
address 0x00 after the t
In suspend mode, only the BOR detection is active, giving a reset
if V
suspended and code is not executing, this lower reset voltage is
safe for retaining the state of all registers and memory. Note that
in suspend mode, LVR is disabled as discussed in Section .
Watchdog Reset (WDR)
CC
START
CC
to stabilize before it begins executing code from address
drops below approximately 2.5V. Since the device is
(see Section for the value of t
LVR
Execution begins at
ROM Address 0x0000
. Therefore, LVR should be enabled at all times
START
START
CC
delay occurs before normal operation
pin voltage drops below V
delay.
CY7C63221/31A
START
CC
). During this t
rises above V
CC
CC
Page 15 of 47
voltage to the
drops and
WATCH
LVR
. The
START
CC
(see
LVR
.
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