CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 24

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Bit 6: IN Received
Bit 5: OUT Received
Bit 4: ACKed Transaction
Bit [3:0]: Mode Bit[3:0]
Bit 7: STALL
Bit [6:5]: Reserved. Must be written to zero during register writes.
Bit 4: ACKed Transaction
Document #: 38-08028 Rev. *D
Read/Write
Read/Write
Bit Name
Bit Name
1 = A valid IN packet has been received. This bit is updated
to ‘1’ after the last received packet in an IN transaction. This
bit is cleared by any non-locked writes to the register.
0 = No IN received. This bit is cleared by any non-locked
writes to the register.
1 = A valid OUT packet has been received. This bit is updated
to ‘1’ after the last received packet in an OUT transaction. This
bit is cleared by any non-locked writes to the register.
0 = No OUT received. This bit is cleared by any non-locked
writes to the register.
The ACKed Transaction bit is set whenever the SIE engages
in a transaction to the register's endpoint that completes with
an ACK packet.
1 = The transaction completes with an ACK
0 = The transaction does not complete with an ACK
The endpoint modes determine how the SIE responds to USB
traffic that the host sends to the endpoint. For example, if the
1 = The SIE will stall an OUT packet if the Mode Bits are set
to ACK-OUT, and the SIE will stall an IN packet if the mode
bits are set to ACK-IN. See Section for the available modes.
0 = This bit must be set to LOW for all other modes.
The ACKed transaction bit is set whenever the SIE engages
in a transaction to the register's endpoint that completes with
an ACK packet.
Reset
Reset
Bit #
Bit #
Data Toggle
STALL
R/W
R/W
7
0
7
0
Figure 17. Endpoint 0 and 1 Counter Registers (Addresses 0x11 and 0x13)
Data Valid
Figure 16. USB Endpoint EP1 Mode Registers (Address 0x14)
R/W
6
0
6
0
-
Reserved
5
0
5
0
-
-
Reserved
Transaction
ACKed
R/C
4
0
4
0
-
USB Non-Control Endpoints
The feature one non-control endpoint, endpoint 1 (EP1). The
EP1 Mode Register does not have the locking mechanism of the
EP0 Mode Register. The EP1 Mode Register uses the format
shown in
0xF0–0xF7 as shown in Section .
Bit [3:0]: Mode Bit [3:0]
USB Endpoint Counter Registers
There are two Endpoint Counter registers, with identical formats
for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as
bits for data packet status. The format of these registers is shown
in Figure 17.
endpoint Mode Bits [3:0] are set to 0001 which is NAK IN/OUT
mode as shown in
in response to any IN or OUT token sent to this endpoint. In
this NAK IN/OUT mode, the SIE will send an ACK handshake
when the host sends a SETUP token to this endpoint. The
mode encoding is shown in
the mode bits can be found in
modes give the firmware total control on how to respond to
different tokens sent to the endpoints from the host.
In addition, the Mode Bits are automatically changed by the
SIE in response to many USB transactions. For example, if
the Mode Bit [3:0] are set to 1011 which is ACK OUT-NAK IN
mode as shown in
Mode Bit [3:0] to NAK IN/OUT (0001) mode after issuing an
ACK handshake in response to an OUT token. Firmware
needs to update the mode for the SIE to respond appropriate-
ly.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
The EP1 Mode Bits operate in the same manner as the EP0
Mode Bits (see Section ).
R/W
R/W
3
0
3
0
Figure
16. EP1 uses an 8-byte FIFO at SRAM locations
Table
R/W
R/W
Table
2
0
2
0
Byte Count
Mode Bit
6, the SIE will send NAK handshakes
6, the SIE will change the endpoint
Table
Table 7
R/W
R/W
CY7C63221/31A
6. Additional information on
1
0
1
0
and
Table
Page 24 of 47
R/W
R/W
0
0
0
0
8. These
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