CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 20

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 3. Ports 0 and 1 Output Control Truth Table
Auxiliary Input Port
Port 2 serves as an auxiliary input port as shown in Figure 12.
The Port 2 inputs all have TTL input thresholds.
Bit [7:6]: Reserved
Bit [5:4]: D+ (SCLK) and D- (SDATA) States
Bit 3: Reserved
Bit 2: P2.2 (Internal Clock Mode Only)
Bit 1: P2.1 (Internal Clock Mode Only)
Document #: 38-08028 Rev. *D
Data Register
The state of the D+ and D– pins can be read at Port 2 Data
Register. Performing a read from the port pins returns their
logic values.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
In the Internal Clock mode, the XTALOUT pin can serve as a
general purpose input, and its state can be read at Port 2, Bit
2 (P2.2). See Section for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
In the Internal Clock mode, the XTALIN pin can serve as a
general purpose input, and its state can be read at Port 2, Bit
1 (P2.1). See Section for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Read/Write
Bit Name
Reset
Bit #
0
1
0
1
0
1
0
1
7
0
-
Reserved
Mode1
0
0
1
1
6
0
-
Figure 12. Port 2 Data Register (Address 0x02)
D+ (SCLK)
Mode0
State
0
1
0
1
R
5
0
D– (SDATA)
State
R
4
0
Output Drive Strength
Bit 0: P2.0/ VREG Pin State
USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the USB
host. The SIE simplifies the interface between the microcon-
troller and USB by incorporating hardware that handles the
following USB bus activity independently of the microcontroller:
■
■
■
■
■
■
Medium (8 mA) Sink
Translate the encoded received data and format the data to be
transmitted on the bus.
CRC checking and generation. Flag the microcontroller if errors
exist during transmission.
Address checking. Ignore the transactions not addressed to
the device.
Send appropriate ACK/NAK/STALL handshakes.
Token type identification (SETUP, IN, or OUT). Set the appro-
priate token bit once a valid token is received.
Place valid received data in the appropriate endpoint FIFOs.
High (50 mA) Sink
Low (2 mA) Sink
In PS/2 mode, the VREG pin can be used as an input and its
state can be read at port P2.0. Section for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
High Drive
High Drive
Resistive
Reserved
Hi-Z
Hi-Z
3
0
-
Clock Mode
(Internal
Only)
P2.2
R
2
0
Clock Mode
CY7C63221/31A
Input Threshold
(Internal
Only)
P2.1
R
1
0
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
TTL
VREG Pin
Page 20 of 47
State
P2.0
R
0
0
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