CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 30

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Bit [5:3]: Reserved
Bit 2: 1.024-ms Interrupt Enable
Bit [7:3]: Reserved.
Bit [2:1]: EP1 Interrupt Enable
Document #: 38-08028 Rev. *D
Read/Write
❐
❐
❐
❐
Bit Name
GPIO edge, while setting a Polarity bit to ‘1’ allows an interrupt
on a rising GPIO edge. The Polarity Registers reset to 0 and
are shown in Figure for Port 0 and Figure 29 for Port 1.
All of the GPIO pins share a single interrupt vector, which
means the firmware will need to read the GPIO ports with
enabled interrupts to determine which pin or pins caused an
interrupt.The GPIO interrupt structure is illustrated in Figure .
Note that if one port pin triggered an interrupt, no other port
pins can cause a GPIO interrupt until that port pin has re-
turned to its inactive (non-trigger) state or its corresponding
port interrupt enable bit is cleared. The CY7C63221/31A does
not assign interrupt priority to different port pins and the Port
Interrupt Enable Registers are not affected by the interrupt
acknowledge process.
1 = Enable
0 = Disable
The 1.024-ms interrupts are periodic timer interrupts from the
free-running timer (based on the 6-MHz clock). The user
should disable this interrupt before going into the suspend
mode to avoid possible conflicts between servicing the timer
interrupts (128-μs interrupt and 1.024-ms interrupt) first or the
suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approximate-
ly every 1.024 ms.
0 = Disable.
The non-control endpoint interrupt (EP1) is generated when:
1 = Enable
0 = Disable
Reset
The USB host writes valid data to an endpoint FIFO. Howev-
er, if the endpoint is in ACK OUT modes, an interrupt is gen-
erated regardless of data packet validity (i.e., good CRC).
Firmware must check for data validity.
The device SIE sends a NAK or STALL handshake packet
to the USB host during the host attempts to read data from
the endpoint (INs).
The device receives an ACK handshake after a successful
read transaction (IN) from the host.
The device SIE sends a NAK or STALL handshake packet
to the USB host during the host attempts to write data (OUTs)
to the endpoint FIFO.
Bit #
7
0
-
Figure 24. Endpoint Interrupt Enable Register (Address 0x21)
6
0
-
5
0
-
Reserved
4
0
-
Bit 1: 128-μs Interrupt Enable
Bit 0: USB Bus Reset - PS/2 Interrupt Enable
Refer to
Bit 0: EP0 Interrupt Enable
❐
❐
❐
❐
❐
The 128-μs interrupt is another source of timer interrupt from
the free-running timer. The user should disable both timer in-
terrupts (128-μs and 1.024-ms) before going into the suspend
mode to avoid possible conflicts between servicing the timer
interrupts first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approximate-
ly every 128 μs.
0 = Disable.
The function of this interrupt is selectable between detection
of either a USB bus reset condition, or PS/2 activity. The se-
lection is made with the USB-PS/2 Interrupt Mode bit in the
USB Status and Control Register (Figure ). In either case, the
interrupt will occur if the selected condition exists for 256 μs,
and may occur as early as 128 μs.
A USB bus reset is indicated by a single-ended zero (SE0) on
the USB D+ and D– pins. The USB Bus Reset interrupt occurs
when the SE0 condition ends. PS/2 activity is indicated by a
continuous LOW on the SDATA pin. The PS/2 interrupt occurs
as soon as the long LOW state is detected.
During the entire interval of a USB Bus Reset or PS/2 interrupt
event, the USB Device Address register is cleared.
The Bus Reset/PS/2 interrupt may occur 128μs after the bus
condition is removed.
1 = Enable
0 = Disable
If enabled, the control endpoint interrupt is generated when:
1 = Enable EP0 interrupt
0 = Disable EP0 interrupt
The endpoint 0 mode is set to accept a SETUP token.
After the SIE sends a 0 byte packet in the status stage of a
control transfer.
The USB host writes valid data to an endpoint FIFO. Howev-
er, if the endpoint is in ACK OUT modes, an interrupt is gen-
erated regardless of what data is received. Firmware must
check for data validity.
The device SIE sends a NAK or STALL handshake packet
to the USB host during the host attempts to read data from
the endpoint (INs).
The device SIE sends a NAK or STALL handshake packet
to the USB host during the host attempts to write data (OUTs)
to the endpoint FIFO.
Table 6
3
0
-
for more information.
2
0
-
Interrupt
Enable
R/W
EP1
CY7C63221/31A
1
0
Interrupt
Enable
Page 30 of 47
R/W
EP0
0
0
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