CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 29

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Interrupt Vectors
The Interrupt Vectors supported by the device are listed in
Table
PS/2 activity), and the lowest priority interrupt is #11 (Wake-up
Timer). Although Reset is not an interrupt, the first instruction
Table 5. Interrupt Vector Assignments
Interrupt Latency
Interrupt latency can be calculated from the following equation:
Interrupt Latency = (Number of clock cycles remaining in the
current instruction) + (10 clock cycles for the CALL instruction) +
For example, if a 5-clock-cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Bit 7: Wake-up Interrupt Enable
Document #: 38-08028 Rev. *D
Read/Write
Bit Name
The internal wake-up timer is normally used to wake the part
from suspend mode, but it can also provide an interrupt when
the part is awake. The wake-up timer is cleared whenever the
Wake-up Interrupt Enable bit is written to a 0, and runs when-
ever that bit is written to a 1. When the interrupt is enabled,
the wake-up timer provides periodic interrupts at multiples of
period, as described in Section .
1 = Enable wake-up timer for periodic wake-up.
0 = Disable and power-off wake-up timer.
Reset
Bit #
5. The highest priority interrupt is #1 (USB Bus Reset /
Interrupt Vector Number
not applicable
Wake-up
Interrupt
Enable
R/W
10
11
1
2
3
4
5
6
7
8
9
7
0
(5 clock cycles for the JMP instruction)
Interrupt
Enable
GPIO
R/W
Figure 23. Global Interrupt Enable Register (Address 0x20)
6
0
5
0
-
ROM Address
0x000C
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000E
0x0010
0x0012
0x0014
0x0016
Reserved
4
0
-
executed after a reset is at ROM address 0x0000, which corre-
sponds to the first entry in the Interrupt Vector Table. Interrupt
vectors occupy 2 bytes to allow for a 2-byte JMP instruction to
the appropriate Interrupt Service Routine (ISR).
Interrupt Service Routine will execute a minimum of 16 clocks
(1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. With a 6 MHz external resonator, internal CPU clock
speed is 12 MHz, so 20 clocks take 20/12 MHz = 1.67 μs.
Interrupt Sources
The following sections provide details on the different types of
interrupt sources.
Bit 6: GPIO Interrupt Enable
Each GPIO pin can serve as an interrupt input. During a reset,
GPIO interrupts are disabled by clearing all GPIO interrupt
enable registers. Writing a ‘1’ to a GPIO Interrupt Enable bit
enables GPIO interrupts from the corresponding input pin.
These registers are shown in Figure 26 for Port 0 and Figure
for Port 1. In addition to enabling the desired individual pins
for interrupt, the main GPIO interrupt must be enabled, as
explained in Section .
The polarity that triggers an interrupt is controlled indepen-
dently for each GPIO pin by the GPIO Interrupt Polarity Reg-
isters. Setting a Polarity bit to ‘0’ allows an interrupt on a falling
3
0
-
128-μs timer interrupt
1.024-ms timer interrupt
USB Endpoint 0 interrupt
USB Endpoint 1 interrupt
Reserved
Reserved
Reserved
Reserved
GPIO interrupt
Wake-up Timer interrupt
Execution after Reset begins here.
USB Bus Reset or PS/2 Activity interrupt
1.024-ms
Interrupt
Enable
R/W
2
0
Function
Interrupt
128-μs
Enable
R/W
CY7C63221/31A
1
0
PS/2 Activity
Intr. Enable
USB Bus
Reset /
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R/W
0
0
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