CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 19

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Bit [7:2]: Reserved
Bit [1:0]: P1[1:0] Mode 0
Bit [7:2]: Reserved
Bit [1:0]: P1[1:0] Mode 1
Each pin can be independently configured as high-impedance
inputs, inputs with internal pull-ups, open drain outputs, or tradi-
tional CMOS outputs with selectable drive strengths.
The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register and by its associated Mode0
and Mode1 bits. Table 3 lists the configuration states based on
these bits. The GPIO ports default on reset to all Data and Mode
Registers cleared, so the pins are all in a high-impedance state.
The available GPIO output drive strength are:
■
■
■
Document #: 38-08028 Rev. *D
Hi-Z Mode (Mode1 = 0 and Mode0 = 0)
Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
Register = 0)
Medium Sink Mode (Mode1 = 0, Mode0 = 1, and the pin’s Data
Register = 0)
1 = Port Pin Mode 0 is logic HIGH
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Q1, Q2, and Q3 (Figure 5) are OFF. The GPIO pin is not driv-
en internally. Performing a read from the Port Data Register
return the actual logic value on the port pins.
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 2 mA of current.
Read/Write
Read/Write
Bit Name
Bit Name
Reset
Reset
Bit #
Bit #
7
0
7
0
-
-
Figure 10. GPIO Port 1 Mode0 Register (Address 0x0C)
Figure 11. GPIO Port 1 Mode1 Register (Address 0x0D)
6
0
6
0
-
-
5
0
5
0
-
-
Reserved
Reserved
4
0
4
0
-
-
■
■
■
Note that open drain mode can be achieved by fixing the Data
and Mode1 Registers LOW, and switching the Mode0 register.
Input thresholds are CMOS, or TTL as shown in the table (See
Section for the input threshold voltage in TTL or CMOS modes).
Both input modes include hysteresis to minimize noise sensi-
tivity. In suspend mode, if a pin is used for a wake-up interrupt
using an external R-C circuit, CMOS mode is preferred for lowest
power.
High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data
Register = 0)
High Drive Mode (Mode1 = 0 or 1, Mode0 = 1, and the pin’s
Data Register = 1)
Resistive Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
Register = 1)
0 = Port Pin Mode 0 is logic LOW
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 8 mA of current.
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 50 mA of current.
Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of
sourcing 2 mA of current.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with
an internal 14-kΩ resistor.
3
0
3
0
-
-
2
0
2
0
-
-
CY7C63221/31A
W
W
1
0
1
0
P1[1:0] Mode0
P1[1:0] Mode1
Page 19 of 47
W
W
0
0
0
0
[+] Feedback