CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 32

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Bit [7:0]: P1 [7:0] Interrupt Enable
Bit [7:0]: P0[7:0] Interrupt Polarity
Bit [7:0]: P1[7:0] Interrupt Polarity
Document #: 38-08028 Rev. *D
Read/Write
Read/Write
Bit Name
Bit Name
1 = Enables GPIO interrupts from the corresponding input pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
1 = Rising GPIO edge
1 = Rising GPIO edge
Reset
Reset
GPIO
Pin
Bit #
Bit #
IRA
1 = Enable
0 = Disable
W
7
0
7
0
-
Port Bit Interrupt
Enable Register
Port Bit Interrupt
Polarity Register
Figure 28. Port 0 Interrupt Polarity Register (Address 0x06)
Figure 29. Port 1 Interrupt Polarity Register (Address 0x07)
W
6
0
6
0
-
M
U
X
Figure 30. GPIO Interrupt Diagram
W
5
0
5
0
-
Reserved
1 = Enable
0 = Disable
P0 Interrupt Polarity
(1 input per
OR Gate
GPIO pin)
W
4
0
4
0
-
(Bit 6, Register 0x20)
GPIO Interrupt
The polarity that triggers an interrupt is controlled independently
for each GPIO pin by the GPIO Interrupt Polarity Registers.
Figure and Figure 29 control the interrupt polarity of each GPIO
pin.
0 = Falling GPIO edge
0 = Falling GPIO edge
Global
Enable
1
W
3
0
3
0
-
GPIO Interrupt
Flip Flop
D
CLR
Q
W
2
0
2
0
-
P1[1:0] Interrupt Polarity
Interrupt
Encoder
Priority
CY7C63221/31A
W
W
1
0
1
0
Page 32 of 47
Interrupt
IRQout
W
W
Vector
0
0
0
0
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