CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet
CY8CTST200-48LTXIT
Specifications of CY8CTST200-48LTXIT
Related parts for CY8CTST200-48LTXIT
CY8CTST200-48LTXIT Summary of contents
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... PSoC CY8CTMG20x, CY8CTMG20xA, CY8CTST200, CY8CTST200A TRM ® PSoC CY8CTMG20x, CY8CTMG20xA, Technical Reference Manual (TRM) CY8CTST200, CY8CTST200A Document No. 001-53603 Rev. *C Phone (USA): 800.858.1810 Phone (Intnl.): 408.943.2600 December 11, 2009 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 [+] Feedback ...
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... Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving Cypress are committed to continuously improving the code protection features of our products system, provided that the system conforms to the I PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev Standard [+] Feedback ...
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Contents Overview Section A: Overview 1. Pin Information .......................................................................................................................... 19 Section B: PSoC Core 2. CPU Core (M8C) ........................................................................................................................ 27 3. Supervisory ROM (SROM) ......................................................................................................... 33 4. RAM Paging ............................................................................................................................... 39 5. Interrupt Controller ..................................................................................................................... 45 6. General Purpose I/O ...
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Contents Overview 4 [+] Feedback ...
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... Contents Section A: Overview 1. Pin Information 1.1 Pinouts....................................................................................................................................19 1.1.1 CY8CTMG200-16LGXI, CY8CTMG200A-16LGXI, CY8CTST200-16LGXI, CY8CTST200A-16LGXI PSoC 16-Pin Part Pinout 19 1.1.2 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI, CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout 20 1.1.3 CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI, CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC 32- Pin Part Pinout21 1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI, CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC ...
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Contents 3.1.2.11 WriteAndVerify Function.............................................................................. 37 3.1.2.12 HWBootReset Function............................................................................... 38 3.2 Register Definitions ................................................................................................................ 38 4. RAM Paging 4.1 Architectural Description......................................................................................................... 39 4.1.1 Basic Paging..............................................................................................................39 4.1.2 Stack Operations ....................................................................................................... 40 4.1.3 Interrupts ................................................................................................................... 40 4.1.4 MVI Instructions......................................................................................................... 40 4.1.5 Current Page ...
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Internal Main Oscillator (IMO) 7.1 Architectural Description.........................................................................................................63 7.2 Application Overview ..............................................................................................................63 7.2.1 Trimming the IMO ......................................................................................................63 7.2.2 Engaging Slow IMO ...................................................................................................63 7.3 Register Definitions.................................................................................................................64 7.3.1 IMO_TR Register .......................................................................................................64 7.3.2 IMO_TR1 Register ....................................................................................................64 7.3.3 CPU_SCR1 Register .................................................................................................65 7.3.4 OSC_CR2 Register ...
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Contents 11.1.1.5 Sigma Delta................................................................................................. 89 11.1.2 IDAC .......................................................................................................................... 90 11.1.3 TrueTouch Counter ................................................................................................... 90 11.1.3.1 Operation .................................................................................................... 91 11.2 Register Definitions ............................................................................................................... 92 11.2.1 CS_CR0 Register ..................................................................................................... 92 11.2.2 CS_CR1 Register ..................................................................................................... 93 11.2.3 CS_CR2 Register ..................................................................................................... 93 11.2.4 CS_CR3 ...
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Register Definitions...............................................................................................................122 15.3.1 I2C_XCFG Register .................................................................................................122 15.3.2 I2C_XSTAT Register................................................................................................123 15.3.3 I2C_ADDR Register.................................................................................................123 15.3.4 I2C_BP Register ......................................................................................................123 15.3.5 I2C_CP Register ......................................................................................................124 15.3.6 CPU_BP Register ....................................................................................................124 15.3.7 CPU_CP Register....................................................................................................124 15.3.8 I2C_BUF Register....................................................................................................125 15.3.9 I2C_CFG Register ..................................................................................................126 15.3.10 I2C_SCR Register ..................................................................................................128 15.3.11 ...
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Contents 18.2 Register Definitions ..............................................................................................................147 18.2.1 SPI_TXR Register ...................................................................................................147 18.2.2 SPI_RXR Register...................................................................................................148 18.2.2.1 SPI Master Data Register Definitions........................................................148 18.2.2.2 SPI Slave Data Register Definitions..........................................................148 18.2.3 SPI_CR Register .....................................................................................................149 18.2.3.1 SPI Control Register Definitions................................................................149 18.2.4 SPI_CFG Register...................................................................................................150 18.2.4.1 SPI Configuration Register ...
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IMO_TR1 Register...................................................................................................181 20.3.16 Related Registers ....................................................................................................181 Section E: Registers 21. Register Reference 21.1 Maneuvering Around the Registers ......................................................................................187 21.2 Register Conventions ...........................................................................................................187 21.3 Bank 0 Registers ..................................................................................................................188 21.3.1 PRTxDR ..................................................................................................................188 21.3.2 PRTxIE ...................................................................................................................189 21.3.3 SPI_TXR .................................................................................................................190 21.3.4 SPI_RXR ................................................................................................................191 ...
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Contents 21.3.46 CUR_PP .................................................................................................................234 21.3.47 STK_PP ..................................................................................................................235 21.3.48 IDX_PP ...................................................................................................................236 21.3.49 MVR_PP .................................................................................................................237 21.3.50 MVW_PP ................................................................................................................238 21.3.51 I2C_CFG ................................................................................................................239 21.3.52 I2C_SCR ................................................................................................................240 21.3.53 I2C_DR ...................................................................................................................241 21.3.54 INT_CLR0 ...............................................................................................................242 21.3.55 INT_CLR1 ...............................................................................................................244 21.3.56 INT_CLR2 ...............................................................................................................246 21.3.57 INT_MSK2 ..............................................................................................................248 21.3.58 INT_MSK1 ..............................................................................................................249 ...
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... The PSoC family consists of many Programmable System-on-Chip with On-Chip Controller devices. The CY8CTMG20x and CY8CTST200 PSoC devices have fixed analog and digital resources in addition to a fast CPU, Flash program memory, and SRAM data memory to support various TrueTouch™ algorithms. For the most up-to-date ordering, pinout, packaging, or electrical specification information, refer to the PSoC device’s data sheet ...
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... A programmable timer to provide periodic interrupts. ■ Clock boost network providing a stronger signal to ■ switches. Full-speed USB interface for USB 2.0 communication ■ with 512 bytes of dedicated buffer memory and an inter- nal 3V regulator. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... Supervisory ROM (SROM) SRAM Interrupt Controller 6/12/24 MHz Internal Main Oscillator (IMO) SYSTEM BUS I2C USB Slave PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C PSoC Core Top-Level Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 8K, 16K, 32K Flash Nonvolatile Memory ...
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... The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development the Cypress Online Store web site at http://www.cypress.com Document History This section serves as a chronicle of the PSoC® CY8CTMG20x, CY8CTMG20xA, CY8CTST200, CY8CTST200A Technical Reference Manual. Technical Reference Manual History Version/ ...
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... Empty, grayed- Reserved bit or group of bits, unless oth- out table cell erwise stated PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Section A: Overview Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘ ...
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... SROM supervisory read only memory SSADC single slope ADC SSC supervisory system call TC terminal count USB universal serial bus WDT watchdog timer WDR watchdog reset XRES external reset PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Description [+] Feedback ...
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... PSoC device’s data sheet 1.1 Pinouts The CY8CTMG20x, CY8CTMG20xA, CY8CTST200, and CY8CTST200A PSoC devices are available in a variety of pack- ages. Every port pin (labeled with a “P”), except for Vss, Vdd, and XRES in the following tables and illustrations, is capable of Digital I/O. ...
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... The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con- nected to ground, it must be electrically floated and not connected to any other signal. 20 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, Description CY8CTST200-24LQXI, CY8CTST200-24LQXI P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C PSoC Device 1 18 P0[ P0[2] QFN 16 P0[0] 3 ...
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... The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI, CY8CTST200A-32LQXI, ...
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... Pin Name No. 41 Power Vdd IOH I P0[7] 45 IOH I P0[5] 46 IOH I P0[3] 47 Power Vss 48 IOH I P0[1] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Devices P2[ P2[4] 34 P2[2] 33 P2[0] 32 P4[2] QFN 31 P4[0] (Top View) 30 P3[6] 29 P3[4] 28 P3[2] 27 P3[0] 26 XRES 25 P1[6] Description Power pin ...
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... The PSoC Core section discusses the core components of a PSoC device with a base part number of CY8CTMG20x or CY8CTST200 and the registers associated with those components. The core section covers the heart of the PSoC device, which includes the M8C microcontroller; SROM, interrupt controller, GPIO, and SRAM paging; multiple clock sources such as IMO and ILO ...
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... Drive Mode 0[7:0] Drive Mode 1[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Data[7:0] Interrupt Enables[7:0] Drive Mode 0[7:0] Drive Mode 0[7:0] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Carry Zero GIE ...
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... An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. C Clearable register or bit(s). R Read register or bit(s). W Write register or bit(s). PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 P1_LOW_ ...
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... Section B: PSoC Core 26 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... SWAP A, SP ■ expr ■ JMP LABEL ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Register Reference chapter on page 187. The F register is read by using address F7h in either register bank. 2.3 Address Spaces The M8C has three address spaces: ROM, RAM, and regis- ters ...
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... MOV A, [X+expr MOV [expr MOV [X+expr MOV [expr], expr MOV [X+expr], expr MOV X, expr MOV X, [expr MOV X, [X+expr] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Instruction Format Flags MOV [expr MOV MOV MOV A, reg[expr MOV A, reg[X+expr MOV [expr], [expr] 60 ...
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... INC Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. Note 2 The number of cycles required by an instruction is increased by one for instructions that span 128 byte page boundaries in the Flash memory space. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Instruction Format Flags INC [expr] ...
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... Destination Indirect Post Increment ( ■ For more information on addressing modes see the PSoC Designer Assembly Language User Guide. , CPL , DEC , INC , RRC , SWAP . These PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Byte 1 8-Bit Data 8-Bit Address CALL , , JC , JNC , JNZ , JZ . This instruction format ...
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... LJMP and LCALL instructions. These instructions change program execution uncondition- ally to an absolute address. The instructions use an 8-bit opcode, leaving room for a 16-bit destination address. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C The second three-byte instruction format, shown in the sec- ond row of Table ...
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... For GIE=1, the M8C sam- ples the IRQ input for each instruction. For GIE=0, the M8C ignores the IRQ. For additional information, refer to the page 254. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Zero ...
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... This allows the data buffer used in the supervisory operation to be located in any SRAM page. (See the RAM Paging chapter on page 39 regarding the MVR_PP and MVW_PP pointers.) PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 187. Table 3-1. List of SROM Functions Function Code Function Name ...
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... SWBootReset, is determined by the value of the IRAMDIS bit in the CPU_SCR1 register. If IRAMDIS is not set, these addresses are initialized to 00h. If IRAMDIS is set, these addresses are not modified by a SWBootReset after a watchdog reset. for more infor- PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... ReadBlock Function The ReadBlock function is used to read 128 contiguous bytes from Flash: a block. The device has Flash PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C and has two hundred fifty-six 128-byte blocks. Valid block IDs are 0x00 to 0xFF. Table 3-6. Flash Memory Organization ...
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... Flash bank, are not affected by the EraseAll. Table 3-13. EraseAll Parameters (05h) Name Address KEY1 0,F8h KEY2 0,F9h PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Description In PSoC Designer Unprotected U = Unprotected Read protect F = Factory upgrade Disable external write R = Field upgrade ...
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... Calibrate0, they perform the same task, which is to transfer the calibration values stored in a special area of Flash to their appropriate registers. What is unique about Calibrate1 is that it calculates a checksum of the calibration PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C IMO 24 MHz USB trim (high Reserved ...
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... Description KEY1 0,F8h RAM 3Ah. KEY2 0,F9h RAM Stack Pointer value+3, when SSC is executed. 3.2 Register Definitions This chapter has no register detail information because there are no registers directly assigned to the Supervisory ROM. 38 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... Bytes 256 Bytes 256 Bytes ISR FFh PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 24. For a quick reference of all PSoC registers in 187. The first three of these areas do not depend upon the CPU_F register's PgMode bits and are covered in the next subsections after Basic Paging ...
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... PgMode bits in the CPU_F register while in an ISR. If the PgMode bits are changed while in an ISR, the pre-ISR value is still restored by the RETI; but if the CUR_PP register is changed in the PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... STK_PP Mode used by SROM functions initiated by the SSC instruction. * PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C After reset, the PgMode bits are set to 00b. In this mode, index memory accesses are forced to SRAM Page 0, just as they are in a PSoC device with only 256 bytes of SRAM. ...
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... CUR_PP, but the address pointed to may be in another SRAM page. See the MVR_PP and MVW_PP register descriptions for more information. For additional information, refer to the page 234. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 24. Bit 1 Bit 0 Access 24. For ...
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... MVI A, [expr] instruction, not to be confused with the MVI [expr], A instruction covered by the MVW_PP reg- ister. This instruction is considered a read because data is transferred from SRAM to the microprocessor's A register (CPU_A). PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 ...
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... MVI [expr], A instruction. The function of this register and the MVI instructions are independent of the SRAM Paging bits in the CPU_F register. For additional information, refer to the page 238. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access Page Bits[2: MVW_PP register on ...
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... GIE is set from ‘0’ to ‘1’ in the CPU Flag register. 2. The current executing instruction finishes. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 5-1, illustrating the concepts of posted interrupts and pending Priority ...
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... A software mechanism is pro- vided to set individual interrupts. Setting an interrupt by way of software is very useful during code development, when Equation 2 one may not have the complete hardware system necessary to generate a real interrupt. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 5-1 clocking The [+] Feedback ...
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... Reset 1 0004h Supply voltage monitor 2 0008h Analog 3 000Ch TrueTouch 4 0010h Timer0 5 0014h GPIO 6 0018h SPI 7 001Ch I2C 8 0020h Sleep Timer 9 0024h Timer1 10 0028h Timer2 23 (Lowest) 005Ch ADC PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Interrupt Name Interrupt Controller 47 [+] Feedback ...
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... Bit 1: Analog. This bit allows posted analog interrupts to be read, cleared, or set. Bit 0: V Monitor. This bit allows posted voltage monitor interrupts to be read, cleared, or set. For additional information, refer to the page 242. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 24. Bit 2 Bit 1 Bit 0 Access Analog ...
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... Endpoint1. Write 0 AND ENSWINT = 0. Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0. No effect. Write 0 AND ENSWINT = 1. No effect. Write 1 AND ENSWINT = 1. Post an interrupt for USB Endpoint1. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 Endpoint1 Endpoint0 ...
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... Write 1 AND ENSWINT = 0. No effect. Write 0 AND ENSWINT = 1. No effect. Write 1 AND ENSWINT = 1. Post an interrupt for USB Endpoint4. For additional information, refer to the page 246. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Endpoint5 Endpoint4 INT_CLR2 register on ...
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... USB Endpoint3 interrupt. Bit 6: Endpoint2. ’0’ is mask USB Endpoint2 interrupt. ‘1’ is unmask USB Endpoint2 interrupt. Bit 5: Endpoint1. ’0’ is mask USB Endpoint1 interrupt. ‘1’ is unmask USB Endpoint1 interrupt. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 ...
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... However, while in an interrupt ser- vice routine, a user may wish to read the INT_VC register to see the next interrupt. When the INT_VC register is written PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 ...
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... For additional information, refer to the page 252. 5.3.9 Related Registers CPU_F on page 254. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C INT_VC register on Interrupt Controller 53 [+] Feedback ...
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... Interrupt Controller 54 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... Architectural Description The GPIO in the CY8CTMG20x, CY8CTST200 devices are all uniform, except that Port 0 and Port 1 GPIO have stronger high drive. In addition to higher drive strength, Port 1 GPIO have an option for regulated output level. These distinctions are discussed in more detail in the section ...
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... Regulated output level can be selected by bits 4 and 5 in the IO_CFG1 register. For 3V output level, the chip Vdd should be greater than 3.1V. For 2.5V output, the chip Vdd should PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... This assumes the other system level enables are on, such as setting the global GPIO interrupt enable and the Global Interrupt Enable. Setting the pin interrupt enable may PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C immediately assert INTO, if the Interrupt mode conditions are already being met at the pin. ...
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... For all bypass modes, the wanted drive mode of the pin ■ must be configured separately for each pin, with the PRTxDM1 and PRTxDM0 registers. Interrupt Occurs Interrupt Occurs PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 6-1 by the Alt Data input, [+] Feedback ...
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... GIPIO pins. Bits InterruptEnables[7:0]. These bits enable the corresponding port pin interrupt. Only four LSB pins are used since this port has four pins. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Core Register Summary on page Core Register Summary on page Bit 5 ...
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... The GPIO provides a default drive mode of high impedance, analog (High Z). This is achieved by forcing the reset state of all PRTxDM1 registers to FFh. For additional information, refer to the page 259, and the PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access ...
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... PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 P1_LOW_ SPICLK_ Range[1:0] THRS ON_P10 Bit 3 P1_LOW_THRS. This bit reduces the threshold volt- age of the P1 port input buffers so that there are no compat- ibility issues when Port 1 is communicating at regulated voltage levels ...
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... General Purpose I/O (GPIO) 62 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... Reserved PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Summary Table of the Core Registers on page Register Reference chapter on page 7.2 Application Overview Device power may be optimized by selecting among the 24, 12 MHz settings using the SLIMO bits in the CPU_SCR1 register in conjunction with associated trim val- ues in the IMO_TR register ...
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... The value in these bits varies the IMO fre- quency: approximately 7.5 kHz/step. When the EnableLock bit is set in the USB_CR1 register, firmware writes to this register are disabled. For additional information, refer to the page 286. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access EraseAll Parameters (05h), on ...
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... OCD mode, the 48 MHz clock is always active. Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the external clock becomes the source for the internal clock tree, SYSCLK, which drives most device clocking functions. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 ...
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... Internal Main Oscillator (IMO) 7.3.5 Related Registers OSC_CR2 Register on page 115. ■ CPU_SCR1 Register on page 137. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... The ILO is trimmed for 32 kHz in production devices. There is no trim for 1 kHz, hence, high variation is expected from nominal value. The block operates by charging a capacitor with a current reference level. Once reached, the capacitor is discharged to ground. This process repeats to provide the oscillator (half) period. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Register 67 [+] Feedback ...
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... The device-specific value, placed in the trim bits of this register at boot time, is based on factory testing. Do not alter the values in the register. For additional information, refer to the page 282. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access Freq Trim[3: ...
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... ECO and ILO operation. If the bit is '0', switch-over to the ECO is locked out. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Register Reference chapter on page 187. Figure 9-1. External Components for the ECO ...
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... Note Transitions between oscillator domains may produce glitches on the 32 kHz clock bus. Functions that require accuracy on the 32 kHz clock should be enabled after the transition in oscillator domains. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Default POR State ILO Active ECO Inactive ...
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... Bit 1 ECO_EXW. The ECO Exists Written bit is used as a status bit to indicate that the ECO EX bit was previously writ- ten to read only. When this bit is a '1' indicates that the ECO_CFG register was written to and is now locked. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 011b – ...
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... External Crystal Oscillator (ECO) 9.3.4 Related Registers OSC_CR0 Register, on page 113. ■ PRTxDR Registers register on page ■ PRTxIE Registers register on page 59. ■ 72 59. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... OSC_SCR0 (SLP_CFG, SLP_CFG2, SLP_CFG3, Internal Configuration Registers) IMO CLK 32 kHz CLK Sleep Timer PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 187. Figure 10-1. Sleep Controller Architecture Control Inputs Wakeup Timer Sleep Control Logic CPU Hold Off 24. For a quick reference of all PSoC reg- ...
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... In standby mode during buzz, if the external supply falls below the LVD limit, an LVD interrupt occurs and initiates the ■ wakeup sequence. In standby mode, if watchdog reset occurs, it first initiates the wakeup sequence. Once the wakeup is done, it resets the ■ system. 74 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... The maximum worst-case duration of the wakeup sequence is 263 µs, based on the minimum specified ILO frequency of 19 kHz, the minimum specified IMO frequency, and the default settings of the SLP_CFG3 register. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 123 – ...
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... SLEEP bit) is exe- cuted interrupt is pending, the sleep instruction is exe- cuted; but as described in Note 1, the sleep instruction is ignored. The first instruction executed after the ISR is the instruction after sleep. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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... SLP_CFG PSSDC[1:0] The Sleep Configuration Register (SLP_CFG) sets the sleep duty cycle. The value placed in this register is based upon factory test- ing. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Summary Table of the Core Registers on page Bit 5 Bit 4 Bit 3 WDSL_Clear[7:0] However, if the sleep timer is very close to its terminal count, the watchdog timeout is closer to two times ...
Page 78
... Wakeup Timer. ‘00’ µs ‘01’ µs ‘10’ µs ‘11’ µs For additional information, refer to the on page 285. CPU_SCR1 Register on page ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access I2C_ON LSO_OFF SLP_CFG2 register Bit 1 Bit 0 ...
Page 79
... SLEEP BRQ BRA PD PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev properly detect and recover from a VDD brown out condi- tion, the configurable buzz rate must be frequent enough to capture the falling edge of VDD. If the falling edge of VDD is too sharp to be captured by the buzz rate, any of the follow- ing actions must be taken to ensure that the device properly responds to a brown out condition ...
Page 80
... Note Valid when ALT_Buzz[1:0] of the SLP_CFG2 register is 00b. Figure 10-4. Buzz Sequence Timing Figure 10-4, “Buzz Sequence Timing,” on page PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Sleep Timer Counts Period (Nominal) 256 8 ms 1024 31 500 µs ...
Page 81
... WD RESET (WDR) PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C After enabled, periodically clear the WDT in firmware. Do this with a write to the RES_WDT register. This write is data independent, so any write clears the watchdog timer. (Note that a write of 38h also clears the sleep timer.) If for any rea- son the firmware fails to clear the WDT within the selected interval, the circuit asserts WDR to the device ...
Page 82
... Sleep and Watchdog 82 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 83
... The figure below displays the top level architecture of the PSoC’s TrueTouch system. Each component of the figure is dis- cussed at length in this section. TRUETOUCH SYSTEM Two Comparators PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Comparators on page ■ PSoC TrueTouch System Analog Reference ...
Page 84
... PRX_ ICAPEN[1:0] MODE ENABLE[7:0] ENABLE[7:0] ENABLE[7:0] ENABLE[7:0] COMPARATOR REGISTERS (page 103) CMP1D CMP0D INN1[1:0] INP0[1:0] CMP1EN CRST1 CDS1 CINT0 LUT1[3:0] for additional information. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access MODE[1: INSEL[2: PXD_EN CIP_EN RO_EN LPF_EN[1: ...
Page 85
... CSCLK TrueTouch Relaxation IMO Clock Select Oscillator (RO) PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 187. 11.1.1.1 Positive Charge Integration In the positive charge integration method, charge on a sense capacitor is integrated onto a larger capacitor, starting from ground. The number of cycles required to reach a tar- ...
Page 86
... In the second RO method, the interval is set by a number of P0[1] cycles of the RO using a 6-bit counter. During this interval, or P0[3] the IMO clocks a 16-bit counter and the final count gives a measure of capacitance. (See PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 11-4.) Figure 11-13.) Pin Enables CS1 ...
Page 87
... This bus contains ripple at the clock fre- quency, which is filtered with a low pass filter leading into the comparator. In addition, the IDAC current is set to the desired value as explained later in this section. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 11-6. Successive Approximation Block Diagram IDAC CS1 ...
Page 88
... CS2 gives a measure Figure 11-10. The hardware supports the use of either pin P0[1] or P0[3] CSN for the external integration capacitor. C INTERNAL PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C CSCLK I OUT CS1 Conn. to Bus CS2 CSN Closed C INTERNAL ...
Page 89
... Figure 11-11. Negative Charge Integration First Phase: Grounding the Sense Capacitor Grounded Open Vr Reference Buffer Closed Comparator Mux Vref Mux PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 11-12. Negative Charge Integration Second Phase: Integrating Charge onto Integration Capacitor s CS1 CS2 CSN Open Vr C EXTERNAL P0[1] or ...
Page 90
... In this configuration, the counters are enabled simultaneously with a write to the Enable bit. Upon terminal count of the 6-bit RO counter, the contents of the 16-bit counter are captured. Changes in this count then indicate capacitance changes. 11-13) is opti- PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 91
... Disabling and reenabling the TrueTouch block restarts the timer. Figure 11-14. RLO Timer Block Diagram Relaxation Oscillator Programmable TrueTouch Timer Clock Register DATA[5:0] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Edge Detect R IOW or BLOCK_EN IOW or BLOCK_EN R IMO ...
Page 92
... MODE[1:0]), the current count is held and read from the counter registers. Toggle the EN bit to ‘0’ and then back to ‘1’ to start a new count. For additional information, refer to the page 211. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 84. Bit 2 Bit 1 Bit 0 Access ...
Page 93
... Bit 3: CIN_EN. This bit enables the negative charge inte- gration capacitor sense approach. This causes the selected sense pin to alternately connect to the analog global bus and ground, at the rate selected by the CLKSEL bits in the CS_CR1 register. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 CLKSEL[1:0] ...
Page 94
... Data[7:0] Bits Data[7:0]. This value contains the current count for the counter high block. Stop this block to read a valid value. For additional information, refer to the page 216. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access LPF_EN[1: CS_CR3 register on ...
Page 95
... CS_TIMER Register Address Name Bit 7 Bit 6 0,A7h CS_TIMER The TrueTouch Timer Register (CS_TIMER) sets the timer count value. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 COHS PPS INM COLM Mask Bits Never modify the interrupt mask bits while the block is enabled ...
Page 96
... IMO clock to be fed as input to the PRS block. PRESCALE_CLK_DIV[2:0] 000 001 010 011 100 101 110 111 For additional information, refer to the page 220. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access FS_EN CS_SLEW register on Bit 2 Bit 1 Bit 0 Access PRESCALE_CLK_DIV[2:0] ...
Page 97
... Figure 11-17. Continuous Timing (Mode = 11) SYSCLK Block Enable Count Enable Count PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 IDACDATA[7:0] Bits IDACDATA[7:0]. The 8-bit value in this register sets the current driven onto the analog global mux bus when the current DAC mode is enabled ...
Page 98
... Low Byte Count High Byte Clock High Byte Count Enable High Byte Count CS_TIMER[5:0] 03h (6-bit) RLO Clock EN Synchronized EN Count 00h RLO_TIMER_TC RLO_TIMER_IRQ Figure 11-19. 6-Bit RLO Timer Operation 03h 02h 01h 00h PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev [+] Feedback ...
Page 99
... I/O Analog Multiplexer This chapter explains the device-wide I/O Analog Multiplexer for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated registers. For a quick reference of all registers in address order, refer to the page 187. 12.1 Architectural Description The CY8CTMG20x and CY8CTST200 PSoC devices con- tain an enhanced analog multiplexer (mux) capability ...
Page 100
... Register Definitions The following registers are only associated with the Analog Bus Mux in the CY8CTMG20x and CY8CTST200 PSoC devices and are listed in address order. Each register description has an associated register table showing the bit structure for that register. Register bits that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘ ...
Page 101
... Comparators This chapter explains the Comparators for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated regis- ters. For a complete table of the comparator registers, refer to the erence of all registers in address order, refer to the 13.1 Architectural Description The CY8CTMG20x and CY8CTST200 PSoC devices contain two comparators designed to support capacitive sensing or other general purpose uses ...
Page 102
... CMP_RDC register. A selection of comparator state may also be driven to an output pin. When disabled, the comparators consume no power. Two active modes provide a full rail-to-rail input range or a somewhat lower power option with limited input range. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 103
... Register Definitions The following registers areassociated with the Comparators in the CY8CTMG20x and CY8CTST200 PSoC devices and are listed in address order. For a complete table of the comparator registers, refer to the page 84. Each register description has an associated register table showing the bit structure for that register. Register bits that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘ ...
Page 104
... A .XNOR. B Ah: 1010: B Bh: 1011: A .OR. B Ch: 1100: A Dh: 1101: A .OR. B Eh: 1110: A. NAND. B Fh: 1111: TRUE For additional information, refer to the page 210. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access CMP0EN CMP_CR0 register on Bit 2 Bit 1 ...
Page 105
... The figure below displays the top-level architecture of the PSoC system resources. Each component of the figure is dis- cussed at length in the chapters that follow. SYSTEM BUS I2C USB Slave PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C SPI on page 145. ■ Programmable Timer on page ■ ...
Page 106
... RX Reg Full Complete Empty Bypass SS_ PROGRAMMABLE TIMER REGISTERS (page 163) DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] USB REGISTERS (page 171) Data Byte[7:0] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access USB_SE_ USB_CLK_ USB_ON P12EN P10D P10EN ...
Page 107
... Data Valid Toggle Data 0,42h EPx_CNT0 Data Valid Toggle Data 0,44h EPx_CNT0 Data Valid Toggle PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 Data Byte[7:0] Data Byte[7:0] Data Byte[7:0] Data Byte[7:0] Data Byte[7:0] Data Byte[7:0] Data Byte[7:0] ...
Page 108
... Read Address[7:0] Read Address[7:0] NAK_INT_EN ACKed Tx NAK_INT_EN ACKed Tx NAK_INT_EN ACKed Tx NAK_INT_EN ACKed Tx NAK_INT_EN ACKed Tx NAK_INT_EN ACKed Tx NAK_INT_EN ACKed Tx NAK_INT_EN ACKed Tx PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Count # : 0 MSB Count # : 0 MSB Count # : 0 MSB Count # : 0 MSB Count ...
Page 109
... One of four sleep intervals may be selected from 1. SLEEP second. See the OSC_CR0 Register tions section of this chapter. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 14.1.1 Internal Main Oscillator The Internal Main Oscillator (IMO) is the foundation upon which almost all other clock sources in the PSoC device are based ...
Page 110
... SYSCLK. Since SYSCLK is already low, the output is immediately disabled. Therefore, the setup time from SYSCLK to disable is one-half SYSCLK. SLEEP PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 14-2, the setting of the EXTCLKEN bit Figure 14-3, the assertion [+] Feedback ...
Page 111
... EXTCLK bit Figure 14-3. Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One IMO External Clock SYSCLK CPUCLK IOW EXTCLK PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C IMO is External clock is disabled. enabled. IMO is External clock is disabled. ...
Page 112
... When this bit is a ‘1’, clocks are not blocked to the USB block. The device responds to USB traffic depending on the other register settings mentioned under in the Full-Speed USB chapter on page For additional information, refer to the ister on page 267. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 106. Bit 1 Bit 0 Access USB_ON USB_CLK_ON ...
Page 113
... Bit 6 1,E0h OSC_CR0 X32ON Disable Buzz The Oscillator Control Register 0 (OSC_CR0) configures various features of internal clock sources and clock nets. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 P0P4D P0P4EN Bit 6: P0P7EN. This bit enables pin P0[7] for output of the signal selected by P0P7D. ‘ ...
Page 114
... MHz for USB operation. For additional information, refer to the Watchdog Period page 276. (Nominal 375 ms 3 sec 63. This offers PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev MHz 24 MHz Internal Main Internal Main External Clock Oscillator Oscillator 1.5 MHz 3 MHz EXTCLK ...
Page 115
... OSC_CR2 Register Address Name Bit 7 Bit 6 1,E2h OSC_CR2 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 CLK48MEN EXTCLKEN The Oscillator Control Register 2 (OSC_CR2) configures various features of internal clock sources and clock nets. Bit 4: CLK48MEN. This is the 48 MHz clock enable bit. ...
Page 116
... High Z (not High 116 Z Analog), such as drive mode 11b with the PRT1DR bit 4 set high. Bit 1: IMODIS. When set, the Internal Main Oscillator (IMO) is disabled. For additional information, refer to the page 278. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C OSC_CR2 register on [+] Feedback ...
Page 117
... Support for clock rates 400 kHz ■ 10-bit addressing (through firmware support) ■ SMBus operation (through firmware support) ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev communications block is a serial processor 2 C registers, refer to the 2 C slave functionality. However, this module provides new features that 2 Figure 15-1 ...
Page 118
... PSoC device time to respond to the events and conditions on the bus. Figure 15 graphical representation of a typical data transfer from the slave perspective block by PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev Data Transfer 2 C-Bus Specification, version 2.1. ACK/NACK STOP ...
Page 119
... I2C_BP, and the current address pointer, I2C_CP. The byte after the base address pointer is written into the location pointed to by the current address pointer value contained in I2C_CP. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 15-3. Slave Operation M8C writes (ACK interrupt is generated on byte I2C_SCR register ...
Page 120
... Write x Bytes to I2C Slave Slave Addr Address( Set Slave Data Pointer Slave Addr Address( Read x Bytes to I2C Slave Slave Addr 120 Data Data(n) Data(n+ Data A P Data(n) Data(n+1) Data(n+ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Data(n+ Legend Slave Master Data(n+ [+] Feedback ...
Page 121
... Figure 15-5. Address Pointer in EZI2C Mode I2C Base Pointer (I2C_BP) 2 Transmit Data I2C Current Pointer Bytes to I2C (I2C_CP) Interface 6 Receive Data Bytes from I2C Interface PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Buffer Module 0 CPU Base Pointer 1 (CPU_BP CPU Current Pointer ...
Page 122
... I2C_DR register to enable the CPU firmware address compare. The functionality of this bit is independent of the data buffering mode. For additional information, refer to the on page 226. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev 106. Bit 2 Bit 1 Bit 0 Access ...
Page 123
... I2C_CP Register). In case of a read, a Start or Restart must be issued and the read location starts with this address and again subsequent PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 Bits 0: Slave Busy. This bit is set upon a hardware address compare and is reset upon the following stop sig- nal ...
Page 124
... Bits CPU Current Pointer[4:0]. This register is set at the same time and with the same value as the Register. Whenever the read, the CPU_CP increments automatically. For additional information, refer to the page 232. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access I2C_BP Register ...
Page 125
... O reads that occur only in EXEC phase are taken as actual I/O reads for this register. So, only the following basic M8C register access instruc- tions may be used for accessing this register: PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Data Buffer[7:0] ...
Page 126
... SDA are high when idle) or only when both SCL and SDA are low. The other option is to change the drive modes of the I pins to be other than open drain mode and then enable the PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access ...
Page 127
... Regardless of the current state, any Start resets the interface and initiates a Receive operation. Any Stop causes the block to revert to an idle state For additional information, refer to the I2C_CFG register on page 239. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev sample 2 C pins ...
Page 128
... It is active high . A ‘1’ sends an ACK and a ‘0’ sends a NACK. A slave receiver sends a NACK to inform the master that it cannot receive any more bytes. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access ...
Page 129
... Byte Complete status bit is set. Data bytes must be read from the I2C_DR register PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C clock in an acknowledge bit from the receiver. Upon the sub- sequent byte complete interrupt, firmware checks the value of this bit. A ‘ ...
Page 130
... CLOCK SCL SCL_IN CLK CTR N 0 SHIFT SDA_IN SDA_OUT 130 I2C_CFG Register. If any of the three divider taps is 2 Figure 15- Input Clocking Two SYSCLKS to first block clock. Figure 15-7. Basic Input/Output Timing . . . . . . . . . PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev [+] Feedback ...
Page 131
... STOP DETECT BUS ERROR and INTERRUPT PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 15-9 shows the timing for Stop status. This bit is set (and the interrupt occurs) two clocks after the synchronized and filtered SDA line transitions to a ‘1’, when the SCL line is high ...
Page 132
... SCL_IN to write to the Figure 15-11. Slave Stall Timing 1 Clocks No STALL STALL Figure 15-12. I2C Wakeup Sequence Send NACK PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C I2C_SCR Register to con- Status Tim- N-1 Clocks No I2C Sleep ...
Page 133
... When this registered signal becomes high, the switch_to_sample_mode signal deasserts asynchronously. d. The state machines and other logic are put at appropriate states when switching to sample mode. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C SCL is released here if buffer mode is enabled, otherwise it is released once CPU is operational and responds by setting the transmit/receive bit ...
Page 134
... I2C Slave 134 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 135
... Control registers (CPU_SCR0 for POR, XRES, and WDR the System Status and Control Register 1 (CPU_SCR1 for IRESS). Firmware can interrogate these registers to determine the cause of a reset. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 106. For a quick reference of all PSoC registers 187. 16.2 ...
Page 136
... After this time, both pins transition to a high impedance state and normal CPU operation begins. This is illustrated in Figure 16-2. P1[1:0] Behavior on External Reset (XRES) XRES P1[0] P1[1] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 16- Sleep Clock Cycles (approximately 200 μs) R0 HiZ ...
Page 137
... Supervisory ROM (SROM) chapter on page Bit 4:3 SLIMO[1:0]. These bits set the IMO frequency range. See the table ahead for more information. These PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C “Summary Table of the System Resource Registers” on page Bit 5 Bit 4 ...
Page 138
... HALT instruction rather than a register write to this bit. For additional information, refer to the on page 258. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access STOP # : XX CPU_SCR0 register ...
Page 139
... Reset Sleep Timer IMO PD IMO (not to scale) CPU Reset PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C During XRES (XRES=1), the IMO is powered off for low power during startup. After XRES deasserts, the IMO is started (see Figure How the XRES configures register reset status bits is shown ...
Page 140
... XRES: Reset while XRES is high (IMO off), then 7(+) cycles (IMO on), and then the CPU reset is released. CLK32 XRES Reset Sleep Timer IMO PD IMO (not to scale) CPU Reset 140 IPOR (Follows POR / XRES PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 511 N=512 7 8 [+] Feedback ...
Page 141
... During and after POR or XRES, the bandgap circuit is pow- ered up. The IMO is always on for at least one CLK32K cycle before CPU reset is deasserted. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Table 16-1. Figure 16-4 on page 140 PPOR (Part of POR) While PPOR=1, plus While POR=1 30-60 µ ...
Page 142
... System Resets 142 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 143
... Other outputs and status bits are provided to indicate important voltage trip levels. Refer to tion 16.2 Pin Behavior During Reset for a description of GPIO pin behavior during power up. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Summary Table of the System Resource Registers on page Register Reference chapter on page 106 ...
Page 144
... Bit 1: LVD. This bit reads the state of the LVD comparator. Zero Vdd is above the trip point. The trip points for LVD are set by VM[2:0] in the VLT_CR register. For additional information, refer to the page 280. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 106. Bit 2 Bit 1 Bit 0 Access ...
Page 145
... The 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. Figure 18-2 signals in a simple connection. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 106. For a quick reference of all PSoC reg- 187. Figure 18-2. Basic SPI Configuration MISO ...
Page 146
... I/O writes to the Port Drive register. 18.1.3.1 Usability Exceptions The following are usability exceptions for the SPI Slave function. The SPI_RXR (RX Buffer) register is not writeable. ■ The SPI_TXR (TX Buffer) register is not readable. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C SPIM Tim- [+] Feedback ...
Page 147
... Bit 7 0,29h SPI_TXR The SPI Transmit Data Register (SPI_TXR) is the SPI’s transmit data register. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 18.1.4 Input Synchronization All pin inputs are double synchronized to SYSCLK by default. Synchronization can be bypassed by setting the BYPS bit in the SPI_CFG register. ...
Page 148
... Receive register. They are discussed by function type in Table 18-2 and For additional information, refer to the page 191. Table 18-2 Description Table 18-3 Description PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Table 18-3. SPI_RXR register on explains the meaning of the Transmit and ...
Page 149
... Read Only 2 Clock Phase Read/Write 1 Clock Polarity Read/Write 0 Enable Read/Write PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 SPI TX Reg RX Reg Full Complete Empty Bit 4: TX Reg Empty. This status bit indicates whether or not the Transmit register is empty. ...
Page 150
... Slave selection determined from SS_ bit Slave selection determined from external SS_ pin Interrupt on TX Reg Empty Interrupt on SPI Complete Operates as a master Operates as a slave. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Int Sel Slave ...
Page 151
... MODE 0, 1 (Phase=0) Input on leading edge. Output on trailing edge. SCLK, Polarity=0 (Mode 0) SCLK, Polarity=1 (Mode 1) MOSI MISO SS_ MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge. SCLK, Polarity=0 (Mode 2) SCLK, Polarity=1 (Mode 3) MOSI MISO SS_ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Figure 18-3. SPI Mode Timing ...
Page 152
... All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and DR2, which are unaffected. Figure 18-4. SPI Input Clocking Two SYSCLKs to first block clock. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 153
... User writes first byte to the TX Buffer register. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C After the last bit is output Buffer data is available with one-half clock setup time to the next clock, a new byte trans- mission is initiated. An SPIM block receives a byte at the same time that it sends one ...
Page 154
... Shifter is loaded edge and is latched with the first byte. into RX Buffer User writes next First input bit First shift. byte to the TX is latched. Buffer register. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Shifter is loaded with the next byte [+] Feedback ...
Page 155
... SS Toggled on Each Byte Transfer in Progress S S SCLK (Mode 0) SCLK (Mode 1) PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C mented as a latch, Overrun status is set one-half bit clock before RX Reg Full status. See Figure 18-7 and Figure 18-8 for status timing relation- ships ...
Page 156
... Last bit of byte is received. All clocks and data for this byte completed. Overrun occurs one- half cycle before the last bit is received. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C User writes the next byte Buffer is transferred into the shifter. ...
Page 157
... User writes first byte to the TX Buffer register in advance of transfer. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C When the block is disabled, the MISO output reverts to its idle 1 state. All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and DR2, which are unaffected ...
Page 158
... TX Buffer register, the byte is loaded into the shifter. The only difference between the modes is that the definition of “transfer in progress” is slightly different between modes 0 and 1, and modes 2 and 3. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Shifter is loaded with the next byte. D1 ...
Page 159
... SCLK in these modes. Figure 18-12. Mode 2 and 3 Transfer in Progress SCLK (Mode 2) SCLK (Mode 3) PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Transfer in Progress Transfer in Progress Transfer in Progress (No Dependance on SS) ...
Page 160
... SPI 160 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 161
... Timer Clock Registers CONFIGURATION[7:0] DATA[7:0] DATA[7:0] PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 106. For a quick reference of all PSoC reg- 187. 19.1.1 Operation When started, the programmable timer loads the value con- tained in its data registers and counts down to its terminal count of zero ...
Page 162
... Count 00h 03h TC IRQ 162 Figure 19-2. Continuous Operation Example 02h 01h 00h 03h 02h 01h TC Period TC Period Figure 19-3. One-Shot Operation Example 02h 01h 00h TC Period PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 00h 03h 02h 01h 00h [+] Feedback ...
Page 163
... START bit in this register is cleared. In con- tinuous mode, the timer reloads the count value each time upon completion of its count cycle and repeats. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Summary Table of the System Resource Registers on Bit 6 Bit 5 ...
Page 164
... PT2_DATA0 register on page Bit 6 Bit 5 Bit 4 Bit 3 DATA[7:0] DATA[7:0] DATA[7:0] For additional information, refer to the on page 222, PT2_DATA1 register on page PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access CLKSEL One Shot START PT2_CFG register on Bit 2 Bit 1 Bit 0 ...
Page 165
... USB pins. The SIE supports nine end- points including a bidirectional control endpoint (endpoint 0) and eight uni-directional data endpoints (endpoints 1 to 8). The uni-directional data endpoints are individually config- urable as either IN or OUT. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Register Reference chapter on page 187. 20.2 Application Description The individual components and issues of the USB system are described in detail in the following sections ...
Page 166
... EP5 10 EP6 11 EP7 12 EP8 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Comments Table 20-2 shows the map- M8C Channel Registers (PMAx_xx) Page 0 PMA0_DR, PMA0_RA, PMA0_WA Page 0 PMA1_DR, PMA1_RA, PMA1_WA Page 0 PMA2_DR, PMA2_RA, PMA2_WA Page 0 PMA3_DR, PMA3_RA, PMA3_WA Page 0 PMA4_DR, PMA4_RA, PMA4_WA ...
Page 167
... While these steps are executed by the M8C, the USB SIE may be fully active on any other PMA channel. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C The M8C may also service another channel and come back to the channel being serviced by the previous steps. To ...
Page 168
... USB Suspend Loss of USB activity, while the USB VBus is still asserted, indicates that the device must enter USB Suspend mode. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0.25%), but it self-tunes to this preci- ± and USBIO_CR1 registers for more ...
Page 169
... These registers are reset after the device comes out of sleep. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C (An alternative is to simply disconnect from the USB bus before going into one of these sleep modes, and then re- connect to re-initialize the USB system after waking up ...
Page 170
... Full-Speed USB Figure 20-2. Transceiver and Regulator Block Diagram VOLTAGE REGULATOR 5V 3.3V TEN TD RECEIVERS PDN RD DPO RSE0 DMO 170 S1 1.5K PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C PS2 Pull TRANSMITTER [+] Feedback ...
Page 171
... Note Set the IMO frequency to 24 MHz and enable the 48 MHz clock in the OSC_CR2 register before USB is enabled. See IMO_TR and CPU_SCR1 registers for selecting IMO frequency as 24 MHz. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Frame Number[7:0] Bits Frame Number ...
Page 172
... USB pull up resistor to D+ pad. Bit 1: DPO. This read only bit gives the state of the D+ pin. Bit 0: DMO. This read only bit gives the state of the D- pin. For additional information, refer to the on page 197. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access ...
Page 173
... While this bit is set to '1', the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data. This bit is cleared by any non-locked writes to the register. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 6 Bit 5 Bit 4 Bit 3 OUT ACK’ ...
Page 174
... Bits Data Byte[7:0]. These registers are shared for both transmit and receive. The count in the EP0_CNT regis- ter determines the number of bytes received trans- ferred. For additional information, refer to the page 200. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Byte Count[3: ...
Page 175
... CRC) received, both the data from the USB packet and the two-byte CRC are written to the USB's dedicated SRAM. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 176
... Bit 0: Count MSB. This bit is the one MSb of a 9-bit counter. The LSb are the Data Count[7:0] bits of the EPx_CNT1 register. Refer to the more information. For additional information, refer to the on page 201. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 2 Bit 1 Bit 0 Access Count MSB # : 0 ...
Page 177
... NAK. ‘0‘ not issue an interrupt after completing the transaction by sending NAK. ‘1‘ is interrupt after transaction is complete by sending NAK. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 ...
Page 178
... PMA channel. In the M8C case, this register always returns the next SRAM address that is used by the PMA channel byte is written to the channel's data register (PMAx_DR) by the M8C. For additional information, refer to the page 263. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access ...
Page 179
... SRAM using the sum of the value of the PMAx_WA register and the USB SIEs received byte count. When the M8C reads this register, a pre-loaded value is returned and the PMAx_RA value is automatically incre- mented. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 180
... Use for Vdd = 3.3V range. '1' is regulating mode. Use for Vdd = 5V range. For additional information, refer to the page 262. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 1 Bit 0 Access ...
Page 181
... Register Details chapter. 20.3.16 Related Registers USB_MISC_CR Register on page 112. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 Bits Fine Trim[2:0]. These bits provide a fine tuning capability to the IMO trim. These three bits are the three LSb of the IMO trim with the IMO_TR register supplying the eight MSb ...
Page 182
... Full-Speed USB 182 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 183
... Logical register or bit(s). C Clearable register or bit(s). # Access is bit specific. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 187. Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is also referred to as I/O space and is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space) ...
Page 184
... PT1_DATA0 PT2_CFG PT2_DATA1 205 PT2_DATA0 206 207 208 210 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev I2C_XCFG C8 RW 226 I2C_XSTAT C9 R 227 I2C_ADDR CA RW 228 I2C_BP CB R 229 I2C_CP CC R 230 CPU_BP CD RW 231 CPU_CP CE R 232 I2C_BUF CF RW 233 ...
Page 185
... PMA6_WA 3A RW 263 PMA7_WA 3B RW 263 PMA0_RA 3C RW 264 PMA1_RA 3D RW 264 PMA2_RA 3E RW 264 PMA3_RA 3F RW 264 Gray fields are reserved # Access is bit specific. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev 264 264 264 264 263 263 263 ...
Page 186
... Section E: Registers 186 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
Page 187
... 0,04h 1, 1,23h x, x,F7h Empty, grayed-out table cell PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Description Multiple instances/address ranges of the same register. Read register or bit(s). Write register or bit(s). Only a read/write register or bit(s). Logical register or bit(s). Clearable register or bit(s). Reset value is 0x00 or 00h. ...
Page 188
... Write value to port or read value from port. Reads return the state of the pin, not the value in the PRTxDR register. 188 PRT2DR : 0,08h Data[7:0] Register Definitions on page 59 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0,00h PRT3DR : 0,0Ch the GPIO chapter. [+] Feedback ...
Page 189
... Name Description 7:0 Interrupt Enables[7:0] These bits enable the corresponding port pin interrupt. Only four LSB are used since this port has four pins PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C PRT2IE : 0,09h Interrupt Enables[7:0] Register Definitions on page 59 in the GPIO chapter. ...
Page 190
... This register is the SPI’s transmit data register. For additional information, refer to the Register Definitions on page 147 Bit Name Description 7:0 Data[7:0] Data for selected function. 190 Data[7:0] in the SPI chapter. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0,29h [+] Feedback ...
Page 191
... This register is the SPI’s receive data register. For additional information, refer to the Register Definitions on page 147 Bit Name Description 7:0 Data[7:0] Data for selected function. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev Data[7:0] in the SPI chapter. SPI_RXR 0,2Ah 0,2Ah ...
Page 192
... Data changes on the leading clock edge. Data is latched on the trailing edge (modes 2, 3). Non-inverted, clock idles low (modes 0, 2). Inverted, clock idles high (modes 1, 3). SPI function is not enabled. SPI function is enabled. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0,2Bh ...
Page 193
... This register is a USB Start-of-Frame register 0. For additional information, refer to the Register Definitions on page 171 Bit Name Description 7:0 Frame Number[7:0] Contains the lower eight bits of the frame number. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev Frame Number[7:0] in the Full-Speed USB chapter. USB_SOF0 0,31h ...
Page 194
... Reserved bits must always be written with a value of ‘0’. For additional information, refer to the page 171 in the Full-Speed USB chapter. Bit Name Description 2:0 Frame Number[10:8] Contains the upper three bits of the frame number. 194 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0,32h Frame Number[10:8] Register Definitions on [+] Feedback ...
Page 195
... USB Enable This bit enables the PSoC device to respond to USB traffic 6:0 Device Address These bits specify the USB address to which the SIE responds. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev Device Address[6:0] in the Full-Speed USB chapter. USB disabled. USB enabled. ...
Page 196
... This bit transmits a USB state on the USB bus. There is no effect if TEN=0 or TSE0= This read only bit gives the state of the USB differential receiver 196 Manual transmission off. Manual transmission enabled. Force USB K state. Force USB J state. D+ < > D-. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0,34h Register Definitions on [+] Feedback ...
Page 197
... This bit controls the connection of the two internal USBPUEN This bit controls the connection of the internal 1 DPO This read only bit provides the D+ pin status. 0 DMO This read only bit provides the D- pin status. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev DPI DMI PS2PUEN in the Full-Speed USB chapter. Ω ...
Page 198
... The mode bits control how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. 198 ACK’ed OUT Received Transaction in the Full-Speed USB chapter. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0,36h Mode[3:0] [+] Feedback ...
Page 199
... This bit selects the data packet's toggle state. 6 Data Valid This bit indicates whether there were errors in OUT or setup transactions. 3:0 Byte Count[3:0] These bits indicate the number of data bytes in a transaction. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev EP0_CNT 0,37h 0,37h ...
Page 200
... Register Definitions on page 171 Bit Name Description 7:0 Data Byte[7:0] These registers are shared for both transmit and receive. 200 EP0_DR2 : 0,3Ah EP0_DR6 : 0,3Eh Data Byte[7:0] in the Full-Speed USB chapter. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 0,38h EP0_DR3 : 0,3Bh EP0_DR7 : 0,3Fh [+] Feedback ...