CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 99

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This chapter explains the device-wide I/O Analog Multiplexer for the CY8CTMG20x and CY8CTST200 PSoC devices and
their associated registers. For a quick reference of all registers in address order, refer to the
page
12.1
The CY8CTMG20x and CY8CTST200 PSoC devices con-
tain an enhanced analog multiplexer (mux) capability. This
function allows many I/O pins to connect to a common inter-
nal analog global bus.
You are able to connect any number of pins simultaneously,
and dedicated support circuitry allows selected pins to be
alternately charged high or connected to the bus. The ana-
log global bus can be connected as a comparator input.
Figure 12-1
system.
Figure 12-1. I/O Analog Mux System
For each pin, the mux capability exists in parallel with the
normal GPIO cell, shown in
ciated GPIO pin is put into a high impedance state for these
applications, although there are cases where the GPIO cell
is configured by the user to briefly drive pin initialization
states as described ahead.
Pins are individually connected to the internal bus by setting
the corresponding bits in the MUX_CRx registers. Any num-
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
12. I/O Analog Multiplexer
IO Pin
IO Pin
187.
Architectural Description
shows a block diagram of the I/O analog mux
Analog Mux Bus
Analog
Device
Mux
Figure
12-2. Normally, the asso-
IO Pin
IO
Pin
ber of pins can be enabled at the same time. At reset, all of
these mux connections are open (disconnected).
Figure 12-2. I/O Pin Configuration
Pin
Before-Make
Circuitry
Break-
GPIO
Register Reference chapter on
Switch Enable
(MUX_CRx.n)
Analog Mux Bus
Discharge
Clock
[+] Feedback
99